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  silicon motion, inc. mobile computer display controller preliminary version 1.5 last updated 2/6/03 SM731 databook

i silicon motion ? , inc. SM731 databook silicon motion ? , inc. SM731 databook notice silicon motion ? , inc. has made best efforts to ensure that the in formation contained in this document is accurate and reliable. however, the information is subject to change without notice. no responsibility is assumed by silicon motion, inc. for the use of this information, nor for infringements of patents or other rights of third parties. copyright notice copyright, 2003 silicon motion, inc. all rights reserved. no part of this publication may be reproduced, photocopied, or transmitted in any form, without the prior written consent of silicon motion, inc. silicon motion, inc. reserves the right to make changes to the product specification without reservation and without notice to our users microsoft ? , windows ? , windows nt ? , and direct3d ? are registered trademarks or tradem arks of microsoft corporation. macrovision ? : this product incorporates copyright protection technology that is protected by u.s. patents and other intellectual property rights. use of this copyright protection technology must be authorized by macrovision, and is intended for home and other limited pay-per-view uses only unless otherwise authorized by macrovision. reverse engineering or disassembly is prohibited version number date note 0.1 10/10/00 all registers are the same as the ly nx3dm except the 3d registers. all registers other than the 3d registers have been included in a single chapter. document includes the new 385-ball bga schematics and ball-diagram. several sections have been temporarily removed until the final details are completed. updated headers and footers. added a numerical ball list. 0.2 11/1/00 added panel registers fpr 100h to fpr 119h. 0.3 1/16/01 completed ball diagram and signal definitions. added lvds registers. 0.4 2/23/01 changed video registers 0.5 3/29/01 updated or changed clock control, vga, power down control, and memory control registers. 0.6 5/1/01 updated 3d section, added 2d3d dma registers, and made changes per engineering specifications. 0.7 8/15/01 updated flat panel registers 0.8 9/25/01 updated 2d drawing engine registers chapter and 2d3d dma registers chapter 1.0 11/20/01 updated databook per engineering specifications 1.1 1/16/02 updated databook per engineering specifications 1.2 2/25/02 updated databook per engineering specifications 1.3 4/1/02 added definitions for ma[6:0] power-on configuration table
ii silicon motion ? , inc. SM731 databook 1.4 7/11/02  changed sm730 to SM731  updated power configuation table  changed pin b7 from ~pme to vpvdd  updated nand tree scan test order  deleted ramdac block diagram  added description for activity output pin (p22)  changed the following registers: ccr65_[4], crt9e_[6], svr4a_[6], svr4c_[7:0], fpr100_[25:24], fpr100_[17:15], fpr100_[10:9], fpr120_[15:0]  added lvds transmitter device transition times diagram and lvds specification table 1.5 2/6/03  remove external memory support, 0/32 mb support, and ddr support.  changed register cpr00, bit 25 to reserved version number date note
table of contents iii silicon motion ? , inc. SM731 confidential databook table of contents chapter 1: overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 chapter 2: initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 SM731 power-on configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 chapter 3: pci/agp bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 pci configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 chapter 4: signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 SM731 ball descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 SM731 nand tree scan testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 nand tree simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 chapter 5: display memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 -1 memory configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 page break look ahead. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 memory timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 chapter 6: 2d drawing engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 chapter 7: display processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 chapter 8: zoom video port and video capture unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 zoom video port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 video capture unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 chapter 9: flat panel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 digital interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 lvds interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 chapter 10: miscellaneous functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 video bios rom interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 vesa dpms interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 i2c bus or vesa ddc2b interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 linear to tile address conversion for cpu access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 chapter 11: clock synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 chapter 12: power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 -1 acpi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 acpi mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 dynamic power management control (dpmc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2-4 activity output pin (p22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 deep sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 chapter 13: motion compensation specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 data flow and external system responsibilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 mc top level architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 mc instruction format and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 chapter 14: 3d drawing engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 dma and command interpreter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 setup engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 rasterizer engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 texture engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 pixel engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 z engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 chapter 15: tv encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 function descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 macrovision antitaping process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 closed captioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
iv table of contents silicon motion ? , inc. SM731 confidential databook sub-carrier generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-5 parallel bus i/f. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-5 chapter 16: power on configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 SM731 power-on configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-1 chapter 17: register overview & usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 register types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-1 pci configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-1 memory mapped i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-1 memory mapped registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-1 mmio write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-2 mmio read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-2 linear memory write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-3 linear memory read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-3 i/o mapped register mapped summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-4 chapter 18: pci configuration space registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 pci configuration space registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-2 extended smi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-11 chapter 19: standard vga registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 standard vga registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-4 general registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-4 sequencer register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-6 crtc controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-9 graphics controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-21 attribute controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-26 ramdac registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-30 chapter 20: extended smi io mapped registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 extended smi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-5 system control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-5 power down control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-14 memory control registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-18 clock control registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-21 general purpose registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-33 pop-up icon and hardware cursor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-36 pop-up icon registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-37 hardware cursor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-40 extended crt control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-42 shadow vga registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-52 chapter 21: flat panel processor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 video processor control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-4 flat panel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-31 chapter 22: crt processor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 video processor control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-3 chapter 23: 2d drawing engine registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 drawing engine control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-3 chapter 24: video capture control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1 capture processor control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-2 linear to tile address conversion for cpu access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7 chapter 25: pci/agp dma control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1 motion comp bus master cmd control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 5-3 motion compensation icmd control registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-6 motion compensation idct control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-8 host master control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-10 texture 3d bus master control registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-13 chapter 26: tv encoder registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 -1 tv decoder register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-2 common register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-2 closed captioning registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-2 chapter 27: 3d registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1 chapter 28: 2d3d dma registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28- 1 dma data header specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28-6
table of contents v silicon motion ? , inc. SM731 confidential databook chapter 29: electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9-1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2 ac timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3 power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3 panel on/off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5 pci bus cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6 agp bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-7 synchronous dram (sdram) and sgram cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-9 flat panel interface cycle timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-10 chapter 30: mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-1 appendix a: video modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 standard ibm compatible vga modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 vesa super vga modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-2 low resolution modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-2 640 by 480 resolution modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-3 800 by 600 resolution modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-3 1024 by 768 resolution modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-4 1280 by 1024 resolution modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-4 appendix b: popup icon consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-1 popup icon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-1 icon pattern memory location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-1 icon pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-1 icon control on crt backend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-2 icon control on lcd backend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-2 video bios function call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-3 enable/disable popup icon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-3 select the size of popup icon. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-3 set popup icon location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-3 set popup icon foreground color . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-4 set popup icon background color . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-4 set popup icon bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-5 appendix c: smi handler programming consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-1 background. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-1 system bios consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-1 int10 vector entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-1 alternate int10 entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-1 appendix d: programming usr [3:0] pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-1 application notes for control of usr [3:0] pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-1 appendix e: monitor and tv detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e- 1 crt monitor detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e-1 tv detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e-1 appendix f: crt and lcd timing register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . f-1 crt timing register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . f-1 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i-1

list of figures vii silicon motion ? , inc. SM731 confidential databook list of figures figure 1. system block diagram for SM731 ...................................................................................... ..... 1-2 figure 2. sgram power-up and initialization sequence....................................................................... 2-1 figure 3. SM731 video bios initialization flow ................................................................................ ..... 2-2 figure 4. SM731 pin diagram for 385 bga package ............................................................................. 4- 8 figure 5. nand tree connection ................................................................................................ ......... 4-10 figure 6. nand tree simulation timing diagram ................................................................................ 4 -10 figure 7. display data source ................................................................................................. ............... 7-1 figure 8. video encoder interface via video port .............................................................................. ..... 8-1 figure 9. video capture block diagram......................................................................................... ......... 8-3 figure 10. video capture data flow............................................................................................ ............. 8-4 figure 11. capture buffer structure in interlaced mode ........................................................................ ... 8-7 figure 12. video bios rom configuration interface ............................................................................. 10-1 figure 13. SM731 i2c bus protocol flow chart .................................................................................. ... 10-3 figure 14. clocks generator block diagram..................................................................................... ...... 11-1 figure 15. mc top level architecture .......................................................................................... .......... 13-2 figure 16. control block diagram .............................................................................................. ............. 13-2 figure 17. qlf block diagram.................................................................................................. .............. 13-3 figure 18. end stream instruction ............................................................................................. ............. 13-4 figure 19. mc instruction format .............................................................................................. ............. 13-4 figure 20. 3d engine .......................................................................................................... .................... 14-2 figure 21. tv encoder block diagram........................................................................................... ......... 15-2 figure 22. i/o port 3c4 ....................................................................................................... .................... 17-4 figure 23. i/o port 3?4....................................................................................................... ..................... 17-4 figure 24. memory mapped address diagram ...................................................................................... .17-5 figure 25. frame buffer memory space.......................................................................................... ....... 17-6 figure 26. power-on reset and reset configuration timing.................................................................. 29-3 figure 27. lvds transmitter device transition times........................................................................... 29-4 figure 28. panel power on..................................................................................................... ................ 29-5 figure 29. panel power off.................................................................................................... ................. 29-5 figure 30. pci bus timing diagram ............................................................................................. .......... 29-6 figure 31. agp bus timing diagram............................................................................................. ......... 29-7 figure 32. agp 2x read request with return data (4qw) ................................................................... 29-8 figure 33. sdram/sgram read and write cycles .............................................................................. 29-9 figure 34. tft interface timing............................................................................................... ............. 29-10 figure 35. 385 bga mechanical dimensions ...................................................................................... ... 30-1 figure 36. hardware cursor and popup icon memory location...............................................................b-1

list of tables ix silicon motion ? , inc. SM731 confidential databook list of tables table 1. power on configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 table 2. ball functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 table 3. signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 table 4. SM731 vcc and ground connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 table 5. nand tree scan test order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 table 6. SM731 video port interface i/o compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 table 7. bit setting summary for video capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 table 8. digital interface pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 table 9. fpdata definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 table 10. dpms summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 table 11. recommended vnr and vdr values for common vclk settings . . . . . . . . . . . . . . . . . . . . . 11-2 table 12. interface signals sleep mode states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 table 13. gated clock trees . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 table 14. instruction flags and parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 table 15. tv encoder block interface description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 table 16. tv encoder sampling rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 table 17. closed captioning lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 table 18. closed captioning odd field output data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 table 19. closed captioning even field output data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 table 20. power on configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 table 21. pci configuration registers quick reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 -1 table 22. standard vga registers quick reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 -1 table 23. extended smi io mapped registers quick reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 table 24. extended smi registers quick reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1-1 table 25. memory mapped video registers quick reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 table 26. drawing engine & capture control registers quick reference . . . . . . . . . . . . . . . . . . . . . . . 23-1 table 27. capture control registers quick reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4-1 table 28. motion comp video registers quick reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1 table 29. tv encoder registers quick reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-1 table 30. 3d registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1 table 31. vertex registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2 table 32. global fog look up table (700-7ff) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3 table 33. 3d registers quick reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3 table 34. summary of 2d 3d dma registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28-3 table 35. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 table 36. digital dc specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 table 37. ramdac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2 table 38. ramdac/clock synthesizer dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2 table 39. ramdac ac specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2 table 40. power-on reset and configuration reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3 table 41. switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4 table 42. lvds specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4 table 43. pci bus timing (33 mhz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6 table 44. agp 1x mode bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-7 table 45. agp 2x timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-7 table 46. agp4x timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-8 table 47. sdram/sgram memory read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-9 table 48. color tft interface timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-10
x list of tables silicon motion ? , inc SM731 confidential databook table 49. standard ibm compatible vga modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 table 50. vesa super vga modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-2 table 51. low resolution modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-2 table 52. 640 x 480 extended modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-3 table 53. 800x600 extended modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-3 table 54. 1024x768 extended modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-4 table 55. 1280x1024 extended modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-4 table 56. 1600x1200 extended modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-5 table 57. crt timing register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . f-1
overview 1 - 1 silicon motion ? , inc. SM731 confidential databook chapter 1: overview the SM731 is a power managed, low-power display controller for portable devices including notebooks and tablet pcs. this device delivers full featured 3d, an unique memory architecture designed to enhance 3d/2d performance, enhanced multi-display capabilities, and motion compensation for dvd. reduceon? is a technology that enab les systems to lower power consumptions, and provides a mechanism to intelligently manage the chip's internal clock core voltage and each major functional block of the graphics chip. by turning off the clock to the block that is not used, the power consumption is significantly reduced during normal operation. thus reduceon provides a method in further reducing the overall system power resulting in longer battery life. the SM731 incorporates an ieee floating point setup engine as well as a full featured 3d rendering engine. the 3d engine pipeline was designed to operate in a balanced manner, allowing setup of 6 million triangles per second (125mhz core frequency) and rasterization of 125 million pixels per second. the dual pipe texture engine can output 250 million texels per second. among other features, SM731 natively supports mip mapping, alpha blend, specular highlights and fog, stencil planes, w buffer and fog, bump mapping, and z engine. the SM731 integrates 16 mbytes of on-board sgram (sdr) over a 64-bit memory bus operating at up to 150 mhz. the total maximum peak bandwidth available (1.2 gbytes/sec) allows concurrent support of large displays and other processing functions at optimum performance. SM731 continues to support all the dual application/dual view capabilities of its predecessors. in addition, SM731 can drive two independent digital displays (dual-digital), as well as simultaneously drive lcd, crt and tv displays (dualmon). SM731 also incorporates two 112 mhz max pix clock lvds channels that can drive two separate panels or a single high resolution panel (up to uxga). the above capabilities are available under windows 98/me, windows 2000, windows xp, and future microsoft operating systems. a robust 128-bit drawing engine provides no compromise 2d performance. the drawing engine supports 3 rops, bitblt, transparent blt, pattern blt, color expansion, line draw and alpha blending. the host interface unit allows support for pci and agp up to 4x with sb signals and over a 1.5v or 3.3v interface. support for all acpi power states is provided. a high quality tv encoder, vga core, lcd backend controller and 235 mhz ramdac are incorporated as well. the SM731's motion compensation block, video processor block, and video capture unit provide superior video quality for real-time video playback and captu re. when combined with performan ce cpus, the motion compensation block allows full frame playback of dvd video content without the need for additional hardware. the video processor supports multiple independent full screen, full motion video windows with overlay. each motion video window uses hardware yuv-to-rgb conversion, scaling, and color interpolation. when combined with multi-view capabilities of the chip, these independent video streams can be output to each of two display devices and bilinear scaled to support applications such as full screen display of local and remote images for video conferencing. SM731 is designed with 0.25m, 5lm, 2.5v cmos process technology. a hierarchical layout approach provides enhanced internal timing control. in addition to built-in test modes and a signature analyzer, the SM731 incorporates a 20 bit test bus which can be used to simultaneously monitor internal signals through the zoom video (zv) port interface. the capability
1 - 2 overview silicon motion ? , inc. SM731 confidential databook can be used to increase fault coverage, and to reduce silicon validation and debugging time. the SM731 is available in a 385-pin bga packages. figure 1: system block diagram for SM731 zv port laserdisc ntsc/pal decoder ntsc/pal camera crt monitor pci/agp2x/4x SM731 16/32mb vcr or tv tv tuner flat panel SM731 16 mb zv port laserdisc ntsc/pal decoder ntsc/pal camera crt monitor pci/agp2x/4x SM731 16/32mb vcr or tv tv tuner flat panel SM731 16 mb
overview 1 - 3 silicon motion ? , inc. SM731 confidential databook microsoft, windows, and direct3d are registered trademarks or trademarks of microsoft corporation. regarding macrovision: this product incorporates copyright pr otection technology that is protect ed by u.s. patents and other i ntellectual property rights. use of this copyright protection technology must be authorized by macrovision, and is intended for home and other limited pay-per-view uses only unless otherwise authorized by macrovision. reverse engineering or disassembly is prohibited. features benefits high performance, power managed 3d desktop level 3d performance within the power budget of a notebook system motion compensation allows full frame playback of dvd content in software dualmon support  applications available at the same time across multiple display devices  single chip implementation ideal for mobile systems dual view support any rectangular portion of primary display can be zoomed up for display on multiple secondary displays dual-digital support independent display support for external digital lcd monitor or lcd projector hardware support for lcd landscape/portrait rotation portrait view for desktop publishing, and word processing applications for tablet pcs. tabview support lcd and crt with different orientations which is key for tablet pcs. (lcd in portrait and crt in landscape) adaptive power management  dynamic functional block shut-down, clock control  reduce average power consumption when in operation mode multiple independent hardware video windows  independent full screen, motion video for separate displays.  complete dual view support for video 128-bit, single clock cycle drawing engine no compromise 2d graphics performance for mobile systems high performance memory interface delivers over 1.2gb/s bandwidth to support 3d graphics, dvd agp 2x/4x sideband and pci 2.1 support provides interface capability for today's most popular pc graphics busses tft panel support up to 1600x1200 with two independent built-in lvds transceiver channels supports all panel requirements for mobile systems integrated tv encoder with macrovision graphics/video display on tv with no external support logic 235mhz 24-bit ramdac supports resolutions up to 1600x1200 zoom video port provides support for camera, tv tuner input, or output to vcr pc99, pc2001 compliant, acpi compliant meets whql certification requirements sw support for microsoft windows 98, windows 2000, windows xp, and linux (xfree86.org) complete os software support

initialization 2 - 1 silicon motion ? , inc. SM731 confidential databook chapter 2: initialization SM731 generates an internal power-on reset during system power-on. after receiving the system ~reset signal, SM731 will release its internal power-on reset circuit and enter the reset period until the host de-asserts the ~reset signal. during the reset period, SM731 resets its internal state mach ines and registers to the power-on default states. during power-on, SM731 is configured based on configuration lines md [37:0]. table 1 provides a detailed description of each configuration line. all md (memory data) lines have internal pull-up resistors on i/o pads which are latched into the corresponding register as logic "1" on the rising edge (trailing edge) of the ~reset. to set a specific bit as logic "0" during power-on reset, an external pull-down resistor must be added on the corresponding md line. in addition to power-on configuration, SM731 performs an initialization sequence for the integrated memory. after memory initialization has been completed, SM731's video bios is ready to service system bios requests. system bios passes a pointer to the SM731 video bios to start the video bios initialization sequence. figure 2: sgram power-up and initialization sequence figure 3 illustrates the SM731 video bios initialization flow. the initialization sequence consists of the following stages:  load configuration table  get panel 2d  initialize int10 function  initialize hardware  query system bios via int 15 calls  set initial mode  enable the display sdck sdcken command nop precharge ma md both banks high-z t=200us t rp load mode register code power-up vcc and sdclk stable precharge program mode register nop auto refresh nop auto refresh nop active bank row t mtc t rc t rc 1st auto refresh cycle 8th auto refresh cycle
2 - 2 initialization silicon motion ? , inc. SM731 confidential databook figure 3: SM731 video bios initialization flow start load default settings (including: set mclk, agp/pci, and panel) read md/ma line settings int 15 ax=7500 get subsystem and subvendor id int 15 ax=7501 get primary panel info. int 15 ax=7502 get secondary panel info. int 15 ax=7503 get initial mode number int 15 ax=7504 get tv info. int 15 ax=7505 get expansion/ centering info. int 15 ax=7506 get banner status int 15 ax=7507 get display status set vga memory size set mode int 15 vga post is done
initialization 2 - 3 silicon motion ? , inc. SM731 confidential databook SM731 power-on configurations  bit md[63:0], ma[11:0], and mba[1:0] have internal pull-up resistors on the i/o pads  0 = external pull-down resistor  1 = no external pull-down resistor table 1: power on configuration signal name read/write register address io address description md[37] config only pll selection. this is a hardware test feature which is used for debug purpose only) definition: pllvck = new,high performance pll pllvrck = existing pll from SM731 pllmck = existing pll from SM731 pllmck2 = new,high performance pll if md[37] config = 1 (default) vclk(video clock) = pllvck vrclk(lcd panel clock) = pllvrck mclk(engine clock) = pllmck mclk2(memory controller clock) = pllmck2 else vclk(video clock) = pllvrck vrclk(lcd panel clock) = pllvrck mclk(engine clock) = pllmck / 2 mclk2(memory controller clock) = pllmck * see also definition of ccr67[3:2] md[36:35] config only size of base memory selection 00=4mb 01=8mb 10=16mb 11=32mb md[34] config only being used when only one endian selected 0=small endian 1=big endian md[33] config only 0=only one endian 1=both endian md[32] reserved md[31] r/w mcr76[7] 3c5.76 0=reserved 1=normal (default) md[30:25] reserved md[24] r/w mcr76[0] 3c5.76 0=sdram interface 1=reserved md[23] 0=and with resetn to reset the free running clock divider for simulation and testing 1=normal (default) md[22} reserved mba[1] config only 0=enable c0000 eprom access 1=disable c0000 eprom access mba[0] config only 0=>pci config reg54[2]=1=>agp4x capable 1=>pci config reg54[2]=0=>not agp4x capable
2 - 4 initialization silicon motion ? , inc. SM731 confidential databook note: for windows xp, windows nt, windows 9x, and windows me, the setting for md [36:35, 33] should be set at [111]. however, for windows ce, the setting for md [36:35, 33] should be set at [1,0,0]. ma[11:8] r/w gpr70[3:0] 3c5.70 panel id 0000 = 640x480 tft 0001 = 800x600 tft 0010 = 1024x768 tft 0011 = 1280x1024 tft 0100 = 1600x1200 tft ma[7] r/w agp pad configuration 0=for 1.5v agp bus 1=for 3.3v agp bus ma[6] r/w lvds interface 0 = 18 bit tft 1 = 24 bit tft ma[5] r/w lvds panel 0 = msb of r,g,b at tx3-+. for 24 bits lvd s 1 = lsb of r,g,b at tx3-+. for 24 bits lvsds (hitachi type) ma[4] r/w panel sequence 0 = software panel on/off sequence 1 = hardware panel on/off sequence ma[3] r/w lvds configuration 0 = use double lvds configuration (two lvds chips on panel side) 1 = use single lvds configuration (only single lvds receiver on panel) ma[2:1] r/w 00=reserved 01=select non-lvds panel as primary panel display 10=select lvds1 as primary panel display 11=both lvds1 and non-lvds panel as primary panel display ma[0] r/w reserved for software purposes md[21:0] reserved signal name read/write register address io address description
pci/agp bus interface 3 - 1 silicon motion ? , inc. SM731 confidential databook chapter 3: pci/agp bus interface SM731 provides a glue-less interface to the pci and agp system bus. the device is fully compliant with pci version 2.2. SM731's pci host interface unit supports both slave and mast er mode. to maximize performance, the host interface unit also supports burst write, and burst read with read lo ok ahead. when connected to the agp interface, SM731 supports agp 2x/4x with sideband. the pci/agp host interface unit manages data transfer betw een the external pci/agp bus and internal host interface (hif) bus. all functional blocks, with the exception of the drawing engine, are tied to the hif bus through a proprietary protocol. separate decode logic and a dedicated fifo are used for the drawing engine. in addition to pci configuration space registers, the pci/agp host interface unit contains power down control registers (pdr20-pdr23) and system control registers (scr10-scr1a). these registers may accessed by the cpu even while internal plls are turned off. pci configuration registers the pci configuration registers are designated csr00 - csr3d. a brief description of key elements of the register set follows:  vendor id register (csr00) - hardwired to 126fh to identify silicon motion, inc. as the chip vendor.  device id register (csr02) - hardwired to 0730h to identify the SM731 device.  status register (csr06) - hardwired to 01b, which indicates medium speed for ~devsel.  class code register (csr08) - hardwired to 030000h to specify SM731 as a vga compatible device. bit [7:0] used to identify the revision of the SM731.  memory base address register (csr10) - specifies the pc i configuration space for address relocation. after power- on, the register defaults to 00h, which indicates the base register can be located anywhere in a 32-bit address space and that the base register is located in memory space.  subsystem vendor id and subsystem id (addressable at csr2c and csr2e respectively) - 32-bit read only registers. these registers are used to differentiate betw een multiple graphics adapters within the same system.

signal descriptions 4 - 1 silicon motion ? , inc. SM731 confidential databook chapter 4: signal descriptions the SM731 is packaged in a 385 bga package. table 2 lists each ball and its associated signal. figure 4 illustrates the pinout diagram for the SM731 package. figure 35 illustrates the mechanical dimensions of the bga package. SM731 ball descriptions the following table, table 2, provides a listing in numerical or der of each ball and its associated signal. table 3, offers a brief description of each signal used by SM731 sorted by functional block. signal names with ~ preceding are active "low" signals, whereas signal names without ~ preceding are active "high" signals. also, the following abbreviations are used for pin type. i - input signal o - output signal i/o - input or output signal ?note: all outputs and i/o signals are tri-stat ed. internal pull-up for i/o pad are all 100k ? resistor. internal pull-down for i/o pad are all 100k ? resistor. table 2: ball functions ball function a1 vss a2 vdd2 a3 md1 a4 md0 a5 md31 a6 md30 a7 ~sip_agp a8 st2 a9 ad2 a10 ad0 a11 vdd3 a12 vdd2 a13 ad12 a14 ad14 a15 ~be0 a16 par a17 ~frame a18 ~be2 a19 ad16 a20 ad18 a21 ad21 a22 vdd2 a23 vss b1 vdd2 b2 vdd3 b3 md2 b4 md3 b5 md28 b6 md29 b7 vpvdd b8 ~agp_busy b9 st1 b10 ad1 b11 ad5 b12 ad4 b13 ad9 b14 ad10 b15 ad13 b16 ~be1 b17 ~trdy b18 ~stop b19 ad17 b20 ad20 b21 ad23 ball function b22 rs2 b23 vdd2 c1 md4 c2 md5 c3 md6 c4 md25 c5 md26 c6 md27 c7 ~rbf c8 ~pipe c9 st0 c10 ad3 c11 ad6 c12 ad7 c13 ad8 c14 ad11 c15 ad15 c16 ~devsel c17 ~irdy c18 ad19 c19 ad22 c20 ~be3 ball function c21 idsel c22 ad24 c23 ad25 d1 md16 d2 md7 d3 md12 d4 md13 d5 md14 d6 dqs0 d7 md15 d8 md24 d9 sba7 d10 sba6 d11 sba5 d12 sba4 d13 sba3 d14 sba2 d15 sba1 d16 sba0 d17 hvref d18 ~sb_stb d19 sb_stb ball function
4 - 2 signal descriptions silicon motion ? , inc. SM731 confidential databook d20 ~ad_stb1 d21 ad26 d22 ad27 d23 ad28 e1 md18 e2 md17 e3 md10 e4 md11 e5 vss e6 vdd2 e7 vss e8 vdd3 e9 vss e10 vdd2 e11 vss e12 hvdd e13 vss e14 hvdd e15 vss e16 vdd1 e17 hvdd e18 vdd2 e19 vss e20 ad_stb1 e21 ad29 e22 ad30 e23 ad31 f1 md19 f2 md20 f3 md8 f4 md9 f5 vdd3 f19 hvdd f20 ad_stb0 f21 ~req f22 ~gnt f23 p0 g1 md22 g2 md21 g3 ~dqm3 g4 mvref g5 vss g19 vss g20 ~ad_stb0 g21 ~rst g22 ~inta g23 p1 h1 ~dqm0 h2 md23 h3 sdcke h4 ~dqm1 h5 vdd2 ball function h19 vdd2 h20 clk h21 p2 h22 p3 h23 p4 j1 ~dqm2 j2 ~we j3 ma8 j4 dsf j5 vss j19 vss j20 p7 j21 p6 j22 p5 j23 pclk k1 ~cas k2 ~ras k3 ~cs k4 ma11 k5 vdd3 k10 vdd3 k11 vdd3 k12 vss k13 vss k14 vdd1 k19 hvdd k20 p9 k21 p11 k22 p8 k23 p12 l1 ma0 l2 ba0 l3 ba1 l4 ma1 l5 vss l10 vdd3 l11 vdd3 l12 vss l13 vss l14 vdd1 l19 vss l20 p13 l21 p15 l22 href l23 p14 m1 vdd2 m2 ma6 m3 ma3 m4 ma2 m5 vdd2 m10 vdd3 m11 vdd2 ball function m12 vss m13 vss m14 vdd1 m19 vpvdd m20 blank m21 palclk m22 p10 m23 rs5 n1 vdd3 n2 ma7 n3 ma5 n4 rs1 n5 vss n10 vdd2 n11 vdd2 n12 vss n13 vss n14 vdd1 n19 vss n20 excken n21 ~pdown n22 mckin n23 vref p1 sdck p2 ~sdck p3 ma9 p4 ma4 p5 vdd3 p10 vdd2 p11 vdd2 p12 vss p13 vss p14 vdd1 p19 vdd2 p20 crthsync p21 crtvsync p22 ~clkrun p23 acon r1 ~dqm7 r2 ~dqm5 r3 ~dqm4 r4 ma10 r5 vss r19 vss r20 usr3 r21 usr2 r22 usr1 r23 usr0 t1 md41 t2 md40 t3 md55 t4 ~dqm6 ball function t5 vdd2 t19 vdd1 t20 rs6 t21 test0 t22 test1 t23 ckin u1 md43 u2 md42 u3 md54 u4 md53 u5 vss u19 vss u20 tvss1 u21 cvdd u22 cvss u23 iref2 v1 md45 v2 md44 v3 md52 v4 md51 v5 vdd3 v19 vdd1 v20 tvdd v21 y v22 c v23 cvbs w1 md47 w2 md46 w3 md50 w4 md49 w5 vss w6 vdd2 w7 rs4 w8 fpvdd w9 vss w10 fpvdd w11 vss w12 fpvdd w13 lvdd2 w14 lvss2 w15 pllvdd w16 pllvss w17 lvss1 w18 lvdd1 w19 vss w20 tvss2 w21 avdd w22 avss2 w23 red y1 md56 y2 md57 y3 md38 ball function
signal descriptions 4 - 3 silicon motion ? , inc. SM731 confidential databook y4 md39 y5 vdd3 y6 md48 y7 ~rom y8 fpde y9 fpsclk y10 fpvsync y11 fd11 y12 fd14 y13 fd15 y14 fd19 y15 tx7- y16 txclk2+ y17 tx6- y18 tx5- y19 tx1- y20 tx2- y21 rs0 y22 iref y23 green aa1 md58 aa2 md59 aa3 md60 aa4 md35 aa5 md36 aa6 md37 aa7 fd2 aa8 fd7 aa9 fphsync aa10 fpvdden1 aa11 fd8 aa12 fd12 aa13 fd16 aa14 fd18 aa15 tx7+ aa16 txclk2- aa17 tx6+ aa18 tx5+ aa19 tx1+ aa20 tx2+ aa21 avss aa22 avss1 aa23 blue ab1 vdd2 ab2 vdd3 ab3 md61 ab4 md32 ab5 md33 ab6 md34 ab7 fd1 ab8 fd4 ab9 fd6 ball function ab10 fpvbiasen1 ab11 fd9 ab12 fd13 ab13 fd17 ab14 fd22 ab15 fpvdden2 ab16 fpen2 ab17 tx4- ab18 tx0- ab19 txclk1+ ab20 tx3- ab21 spnlcki ab22 vdd1 ab23 rs3 ac1 vss ac2 vdd2 ac3 md62 ac4 md63 ac5 dsq1 ac6 fpen1 ac7 fd0 ac8 fd3 ac9 fd5 ac10 fd10 ac11 vdd2 ac12 vdd1 ac13 fd20 ac14 fd21 ac15 fpvbiasen2 ac16 fd23 ac17 tx4+ ac18 tx0+ ac19 txclk1- ac20 tx3+ ac21 spnlcko ac22 vdd1 ac23 vss ball function
4 - 4 signal descriptions silicon motion ? , inc. SM731 confidential databook table 3: signal descriptions signal name type pull-up/ pull-down iol (ma) max. load (pf) description host interface (pci or agp) ad [31:0] i/o tbd 120 multiplexed address and data bus. a bus transaction consists of an address cycle followed by one or more data cycles. ~be [3:0] i/o tbd 120 bus command and byte enables. these signals carry the bus command during the address cycle and byte enable during data cycles. par i/o tbd 120 parity. SM731 asserts this signal to verify even parity across ad [31:0] and c/~be [3:0]. ~frame i/o tbd 120 cycle frame. SM731 asserts this signal to indicate the beginning and duration of a bus transaction. it is de- asserted during the final data cycle of a bus transaction. ~trdy i/o tbd 120 target ready. a bus data cycle is completed when both ~irdy and ~trdy are asserted on the same cycle. ~irdy i/o tbd 120 initiator ready. a bus data cycle is completed when both ~irdy and ~trdy are asserted on the same cycle. ~stop i/o tbd 120 stop. SM731 asserts this signal to indicate that the current target is requesting the master to stop current transaction. ~devsel i/o tbd 120 device select. SM731 asserts this signal when it decodes its addresses as the target of the current transaction. idsel i id select. this input is used during pci configuration read/write cycles. clk i system clock, 33mhz. for pci and 66mhz for agp ~rst i system reset. SM731 asserts this signal to force registers and state machines to initial default values ~req o tbd 120 bus request (bus master mode) ~gnt i bus grant (bus master mode) ~inta o tbd 120 interrupt ~pipe o tbd 120 pipe signal. initiates pipelined agp request. signal indicates beginning and duration of pipelined agp access. ~rbf o tbd 120 read buffer full. indicates if graphics device can accept previously low priority read data ad_stb[1:0] i/o tbd 120 address strobes for agp 2x, 4x transfer support ~ad_stb[1:0] i/o tbd 120 inverted address strobes 1, 0 st[2:0] i status bus for agp support sba[7:0] o tbd 120 sideband address bits 7-0 sb_stb o tbd 120 sideband strobe ~sb_stb o tbd 120 inverted sideband strobe ~agp_busy o tbd 120 power management signal for agp bus. ~stp_agp i power management signal for agp bus. hvref i host bus voltage reference (agp bus voltage)
signal descriptions 4 - 5 silicon motion ? , inc. SM731 confidential databook power down interface ~pdown i pull-up deep power down mode enable. when pdown = 0  all plls are shut down  all agp/pci pads except clk and rst pads are power down when in deep power down mode SM731 will not respond to any host bus cycle  pdown = 1 (default) is the normal setting ~clkrun/ activity o pull-up tbd 60 ~clkrun or SM731 memory and i/o activity detection depending on scr18 [7] 0 = select ~clkrun 1 = select activity acon i pull-up 1 = ac power supply is connected clock interface palclk i pull-up 27mhz clock source for pal tv ckin i pull-up 14.318mhz clock (~excken = 1) or video clock (~excken = 0) mckin/ tmdsclk i/o pull-up tbd 60 memory clock in (~excken = 0) or tmdsclk out (~excken = 1). tmdsclk is a free running clock which can be used to drive a tmds transmitter for dvi interface implementation. note: this pin is used as a secondary clock source for dual panel configuration. for this case configure as tmdsclk. ~excken i pull-up 60 external clock enable. select external vclk from ckin and mclk from mckin. spnlclko o tbd 20 vrclk pll clock out used as input to optional, external spread spectrum inducer ic. spnlclki i pull-down vrclk clock tree input, connected to optional, external spread spectrum inducer ic. flat panel interface fdata [23:0] o pull-down tbd 50 flat panel data bits 23 to 0 for direct connection to 18 or 24 bbp panel or to external tmds transceiver. these lines can be programmed to convey information from the panel controller (primary display source) or the crt controller (secondary display source). single pixel per clock mode support only. fdata[23:22], fdata[14:15] and fdata[6:7] are driven low if panel type is set to 18 bpp. fphsync o pull-down tbd 50 horizontal sync signal from panel controller (primary display source) or crt controller (secondary source). fpvsync o pull-down tbd 50 vertical sync signal from panel controller (primary display source) or crt controller (secondary source). fpde o pull-down tbd 50 display enable signal from panel controller (primary display source) or crt controller (secondary source). this signal is used to indicate the active horizontal display time. fpsclk o pull-down tbd 50 flat panel shift clock. this is the pixel clock for flat panel data. signal name type pull-up/ pull-down iol (ma) max. load (pf) description
4 - 6 signal descriptions silicon motion ? , inc. SM731 confidential databook fpen2 o pull-down tbd 20 flat panel enable. this signal needs to become active after all panel voltages, clocks, and data are stable. this signal also needs to become inactive before any panel voltages or control signals are removed. fpen is part of the vesa fpdi-1b specification. panel controller or crt controller can be timing source. fpvdden2 o pull-down tbd 20 flat panel vdd enable. this signal is used to control lcd panel power. panel controller or crt controller can be timing source. fpvbiasen2 o pull-down tbd 20 flat panel voltage bias enable. this signal is used to control lcd bias power. panel controller or crt controller can be timing source. lvds1 interface tx[3:0]+, tx[3:0]- o lvds1 transmitter encoded data differential pairs. data source is always from panel controller (primary display). txclk1+, txclk1- o lvds1 transmitter encoded clock differential pair. source is always virtual_clock, from panel controller (primary display). fpen1 o flat panel enable. this signal needs to become active after all panel voltages, clocks, and data are stable. this signal also needs to become inactive before any panel voltages or control signals are removed. timing source is always from panel controller fpvdden1 o flat panel vdd enable. this signal is used to control lcd panel power. timing source is always from panel controller. fpvbiasen1 o flat panel voltage bias enable. this signal is used to control lcd bias power. timing source is always from panel controller. lvds2 interface tx[7:4]+, tx[7:4]- o lvds2 transmitter encoded data differential pairs. data source panel controller (primary display) or crt controller (secondary display). txclk2+, txclk2- o lvds2 transmitter encoded clock differential pair. source is virtual_clock, from panel controller (primary display) or video clock, from crt controller (secondary display). crt interface red o analog red current output green o analog green current output blue o analog blue current output iref i current reference input crtvsync o pull-down tbd 50 crt vertical sync crthsync o pull-down tbd 50 crt horizontal sync tv interface y o luminance output c o chrominance output cvbs o composite video output signal name type pull-up/ pull-down iol (ma) max. load (pf) description
signal descriptions 4 - 7 silicon motion ? , inc. SM731 confidential databook iref2 i current reference input video port interface p [15:0] i/o pull-down tbd 20 rgb or yuv input/ rgb digital output pclk i/o pull-up tbd 20 pixel clock vref i/o pull-up tbd 20 vsync input from pc card or video decoder href i/o pull-up tbd 20 hsync input from pc card or video decoder blank o pull-up tbd 20 blank output 0 = blank output general purpose registers / i2c usr3 i/o pull-up tbd 20 general purpose i/o usr2 i/o pull-up tbd 20 general purpose i/o usr1 / sda i/o pull-up tbd 20 general purpose i/o. usr1/ ddc2/ i2c data for crt. can be used to select different test modes. usr0 / scl i/o pull-up tbd 20 general purpose i/o. usr0/ ddc2/ i2c clock for crt. can be used to select different test modes. test mode pins test [1:0] i pull-down test mode selects reserved rs[6:0] reserved - do not connect signal name type pull-up/ pull-down iol (ma) max. load (pf) description
4 - 8 signal descriptions silicon motion ? , inc. SM731 confidential databook figure 4: SM731 pin diagram for 385 bga package 1234567891011121314151617181920212223 a vss vdd2 md1 md0 md31 md30 ~sip_ agp st2 ad2 ad0 vdd3 vdd2 ad12 ad14 ~be0 par ~fra me ~be2 ad16 ad18 ad21 vdd2 vss a b vdd2 vdd3 md2 md3 md28 md29 vpvdd ~agp_ busy st1 ad1 ad5 ad4 ad9 ad10 ad13 ~be1 ~trdy ~stop ad17 ad20 ad23 rs2 vdd2 b c md4 md5 md6 md25 md26 md27 ~rbf ~pipe st0 ad3 ad6 ad7 ad8 ad11 ad15 ~dev sel ~irdy ad19 ad22 ~be3 idsel ad24 ad25 c d md16 md7 md12 md13 md14 dqs0 md15 md24 sba7 sba6 sba5 sba4 sba3 sba2 sba1 sba0 hvref ~sb_s tb sb_st b ~ad_s tb1 ad26 ad27 ad28 d e md18 md17 md10 md11 vss vdd2 vss vdd3 vss vdd2 vss hvdd vss hvdd vss vdd1 hvdd vdd2 vss ad_s tb1 ad29 ad30 ad31 e f md19 md20 md8 md9 vdd3 hvdd ad_s tb0 ~req ~gnt p0 f g md22 md21 ~dqm3 mvref vss SM731 pinout vss ~ad_s tb0 ~rst ~inta p1 g h ~dqm0 md23 sdcke ~dqm1 vdd2 vdd2 clk p2 p3 p4 h j ~dqm2 ~we ma8 dsf vss vssp7p6p5pclk j k ~cas ~ras ~cs ma11 vdd3 vdd3 vdd3 vss vss vdd1 hvdd p9 p11 p8 p12 k l ma0 ba0 ba1 ma1 vss vdd3 vdd3 vss vss vdd1 vss p13 p15 href p14 l m vdd2 ma6 ma3 ma2 vdd2 vdd3 vdd2 vss vss vdd1 vpvdd blank pa l c l k p10 rs5 m n vdd3 ma7 ma5 rs1 vss vdd2 vdd2 vss vss vdd1 vss exck en ~pdo wn mckin vref n p sdck ~sdck ma9 ma4 vdd3 vdd2 vdd2 vss vss vdd1 vdd2 crth sync nc crtv sync ~clk run acon p r ~dqm7 ~dqm5 ~dqm4 ma10 vss vss usr3 usr2 usr1 usr0 r t md41 md40 md55 ~dqm6 vdd2 top view vdd1 rs6 test0 test1 ckin t u md43 md42 md54 md53 vss vss tvss1 cvdd cvss iref2 u v md45 md44 md52 md51 vdd3 vdd1 tvdd y c cvbs v w md47 md46 md50 md49 vss vdd2 rs4 fpvdd vss fpvdd vss fpvdd lvdd2 lvss2 pllvdd pllvss lvss1 lvdd1 vss tvss2 avdd avss2 red w y md56 md57 md38 md39 vdd3 md48 ~rom fpde fpsc lk fpvs ync fd11 fd14 fd15 fd19 tx7- txclk 2+ tx6- tx5- tx1- tx2- rs0 iref green y aa md58 md59 md60 md35 md36 md37 fd2 fd7 fphs ync fpvd den1 fd8 fd12 fd16 fd18 tx7+ txclk 2- tx6+ tx5+ tx1+ tx2+ avss avss1 blue aa ab vdd2 vdd3 md61 md32 md33 md34 fd1 fd4 fd6 fpvbia sen1 fd9 fd13 fd17 fd22 fpvdd en2 fpen2 tx4- tx0- txcl k1+ tx3- spnl cki vdd1 rs3 ab ac vss vdd2 md62 md63 dqs1 fpen 1 fd0 fd3 fd5 fd10 vdd2 vdd1 fd20 fd21 fpvbia sen2 fd23 tx4+ tx0+ txcl k1- tx3+ spnl cko vdd1 vss ac 1234567891011121314151617181920212223
signal descriptions 4 - 9 silicon motion ? , inc. SM731 confidential databook table 4: SM731 vcc and ground connections vcc pin location supply voltage description avdd w21 3.3v crt dac analog power cvdd u21 2.5v clock pll analog power fpvdd w8, w10, w12 3.3v flat panel interface vdd hvdd e12,e14,e17,f19,k19 3.3v/1.5v for agp4x host interface vdd lvdd1 w18 2.5v lvds core vdd lvdd2 w13 2.5v lvds core vdd pllvdd w15 2.5v lvds pll analog power tvdd v20 3.3v tv dac power vpvdd m19, b7 3.3v zv port interface vdd and 3.3 agp pad vdd vdd1 e16, k14, l14, m14, n14, p14, t19, v19, ab22, ac12, ac22 2.5v core vdd vdd2 a2, a12, a22, b1, b23, e6, e10, e18, h5, h19, m1, m5, m11, n10, n11, p10, p11, p19, t5, w6, ab1, ac2, ac11 2.5v/3.3v* memory i/o power vdd3 a11, b2, e8, f5, k5, k10, k11, l10, l11, m10, n1, p5, v5, y5, ab2 2.5v/3.3v* memory core power gnd pin location supply voltage description ground avss aa21 dac analog ground avss1 aa22 dac analog ground avss2 w22 dac analog ground cvss u22 clock pll analog ground lvss1 w17 lvds core ground lvss2 w14 lvds core ground pllvss w16 lvds pll analog ground tvss1 u20 tv dac ground tvss2 w20 tv dac ground vss a1, a23, e5, e7, e9, e11, e13, e15, e19, g5, g19, j5, j19, k12, k13, l5, l12, l13, l19, m12, m13, n5, n12, n13, n19, p12, p13, r5, r19, u5, u19, w5, w9, w11, w19, ac1, ac23 digital ground
4 - 10 signal descriptions silicon motion ? , inc. SM731 confidential databook SM731 nand tree scan testing the SM731 nand tree scan test circuit is designed for verifying the device being properly soldered to the board (nand support for sm721 only). it detects opened/shorted traces of a signal pin with a simple test pattern which, for this particular case, only ~243 vectors in length. since the nand tr ee scan test circuit uses comb ination logic; therefore, no clock pulses are required during the testing. general information the SM731 nand tree scan test circuit is a long chain of 2-input nand gates. the first pin of the nand chain is an input (signal pin "~romen"), the last pin of the chain is an output (signal pin "blank"). in order to setup SM731 for nand tree testing, usr[3:0] pins are programmed to 0010h and test[1:0] pins to 10h. all vdd's, vss's, and analog pins red, green, blue, iref, c, y, cvbs, iref2 are not included in the scan chain. figure 5: nand tree connection nand tree simulation in order to setup SM731 to nand tree scan test mode, usr[3:0] and test[1:0] pins are programmed to 0010h and 10h respectively. in nand tree mode, internal signal testmode6 is a "1" (active "high" signal). in the beginning of the simulation, all inputs are fo rced to "1". then, follow the nand tree pad sequence and change each input to "0" every 400ns, starting with input_0 (signal "~romen"). the output pin (signal "blank") should be a clock waveform that toggles every 400ns (a 2.5mhz square waveform) (see figure 6). any mismatch in the waveform would mean the device was not properly soldered to the board. figure 6: nand tree simulation timing diagram testmode 6 pad_input 1 pad_input 2 pad_input 3 pad_input n nandtree_out (to capture block) testmode6 input #1 (~romen) input #2(md31) input #3 (md0) input #4(md30) input #5 (md1) input #6(md29) input #7 (md2) input #8(md28) output (blank)
signal descriptions 4 - 11 silicon motion ? , inc. SM731 confidential databook table 5: nand tree scan test order nand tree scan pin order# pin name in/out 1stopagpin 2rbfnin 3 agpbusyn in 4 pipen in 5st0in 6st1in 7st2in 8 sba_[7] in 9 sba_[6] in 10 sba_[5] in 11 sba_[4] in 12 sba_[3] in 13 sba_[2] in 14 sba_[1] in 15 sba_[0] in 16 pciad_[0] in 17 pciad_[1] in 18 pciad_[2] in 19 pciad_[3] in 20 pciad_[4] in 21 pciad_[5] in 22 pciad_[6] in 23 pciad_[7] in 24 pciad_[8] in 25 pciad_[9] in 26 pciad_[10] in 27 pciad_[11] in 28 pciad_[12] in 29 pciad_[13] in 30 pciad_[14] in 31 pciad_[15] in 32 cbe_[3] in 33 cbe_[2] in 34 cbe_[1] in 35 cbe_[0] in 36 devsel in 37 irdyn in 38 trdyn in 39 pcipar in 40 stopn in 41 framen in
4 - 12 signal descriptions silicon motion ? , inc. SM731 confidential databook 42 pciclk in 43 adstbn_1 in 44 adstb_1 in 45 adstbn_0 in 46 adstb_1 in 47 sbstbn in 48 sbstb in 49 idsel in 50 pciad_16 in 51 pciad_17 in 52 pciad_18 in 53 pciad_19 in 54 pciad_20 in 55 pciad_21 in 56 pciad_22 in 57 pciad_23 in 58 pciad_24 in 59 pciad_25 in 60 pciad_26 in 61 pciad_27 in 62 pciad_28 in 63 pciad_29 in 64 pciad_30 in 65 pciad_31 in 66 pcireqn in 67 pcigntn in 68 pcirstn in 69 intan in 70 activity in 71 vpdata_0 in 72 vpdata_1 in 73 vpdata_2 in 74 vpdata_3 in 75 vpdata_4 in 76 vpdata_5 in 77 vpdata_6 in 78 vpdata_7 in 79 vpdata_8 in 80 vpdata_9 in 81 vpdata_10 in 82 vpdata_11 in 83 vpdata_12 in nand tree scan pin order# pin name in/out
signal descriptions 4 - 13 silicon motion ? , inc. SM731 confidential databook 84 vpdata_13 in 85 vpdata_14 in 86 vpdata_15 in 87 vphsync in 88 vpvsync in 89 vpclk in 90 palclk in 91 xmck in 92 acon in 93 enxclk in 94 crthsync in 95 crtvsync in 96 spnlcki in 97 spnlck0 in 98 xvck in 99 vbiasen2 in 100 fpvdden2 in 101 fpen2 in 102 fpdata_23 in 103 fpdata_22 in 104 fpdata_21 in 105 fpdata_20 in 106 fpdata_19 in 107 fpdata_18 in 108 fpdata_17 in 109 fpdata_16 in 110 fpdata_15 in 111 fpdata_14 in 112 fpdata_13 in 113 fpdata_12 in 114 vbiasen in 115 fpvdden in 116 fpen in 117 fpde in 118 fpsclk in 119 fpvsync in 120 fphsync in 121 fpdata_11 in 122 fpdata_10 in 123 fpdata_9 in 124 fpdata_8 in 125 fpdata_7 in nand tree scan pin order# pin name in/out
4 - 14 signal descriptions silicon motion ? , inc. SM731 confidential databook 126 fpdata_6 in 127 fpdata_5 in 128 fpdata_4 in 129 fpdata_3 in 130 fpdata_2 in 131 fpdata_1 in 132 fpdata_0 in 133 memrom in 134 extmemdata_63 in 135 extmemdata_62 in 136 extmemdata_61 in 137 extmemdata_60 in 138 extmemdata_59 in 139 extmemdata_58 in 140 extmemdata_57 in 141 extmemdata_56 in 142 extmemdata_55 in 143 extmemdata_54 in 144 extmemdata_53 in 145 extmemdata_52 in 146 extmemdata_51 in 147 extmemdata_50 in 148 extmemdata_49 in 149 extmemdata_48 in 150 extmemdqs1 in 151 extmemdata_47 in 152 extmemdata_46 in 153 extmemdata_45 in 154 extmemdata_44 in 155 extmemdata_43 in 156 extmemdata_42 in 157 extmemdata_41 in 158 extmemdata_40 in 159 extmemdata_39 in 160 extmemdata_38 in 161 extmemdata_37 in 162 extmemdata_36 in 163 extmemdata_35 in 164 extmemdata_34 in 165 extmemdata_33 in 166 extmemdata_32 in 167 extmemdqm_7 in nand tree scan pin order# pin name in/out
signal descriptions 4 - 15 silicon motion ? , inc. SM731 confidential databook 168 extmemdqm_6 in 169 extmemdqm_5 in 170 extmemdqm_4 in 171 extmemdsf in 172 extmemwen in 173 extmemcasn in 174 extmemrasn in 175 extmemcsn in 176 extmemcke in 177 extmemba_1 in 178 extmemba_0 in 179 extmemsclkn in 180 extmemsckp in 181 extmemma_11 in 182 extmemma_10 in 183 extmemma_9 in 184 extmemma_8 in 185 extmemma_7 in 186 extmemma_6 in 187 extmemma_5 in 188 extmemma_4 in 189 extmemma_3 in 190 extmemma_2 in 191 extmemma_1 in 192 extmemma_0 in 193 extmemdqm_3 in 194 extmemdqm_2 in 195 extmemdqm_1 in 196 extmemdqm_0 in 197 extmemdata_31 in 198 extmemdata_30 in 199 extmemdata_29 in 200 extmemdata_28 in 201 extmemdata_27 in 202 extmemdata_26 in 203 extmemdata_25 in 204 extmemdata_24 in 205 extmemdata_23 in 206 extmemdata_22 in 207 extmemdata_21 in 208 extmemdata_20 in 209 extmemdata_19 in nand tree scan pin order# pin name in/out
4 - 16 signal descriptions silicon motion ? , inc. SM731 confidential databook 210 extmemdata_18 in 211 extmemdata_17 in 212 extmemdata_16 in 213 extmemdqs_0 in 214 extmemdata_15 in 215 extmemdata_14 in 216 extmemdata_13 in 217 extmemdata_12 in 218 extmemdata_11 in 219 extmemdata_10 in 220 extmemdata_9 in 221 extmemdata_8 in 222 extmemdata_7 in 223 extmemdata_6 in 224 extmemdata_5 in 225 extmemdata_4 in 226 extmemdata_3 in 227 extmemdata_2 in 228 extmemdata_1 in 229 extmemdata_0 in nand tree scan pin order# pin name in/out
display memory interface 5 - 1 silicon motion ? , inc. SM731 confidential databook chapter 5: display memory interface memory configuration the SM731 memory interface is 64-bits wide and is clocked at 150 mhz, for a total bandwidth of 1.2gb/s peak. the SM731 supports both single and double data rate sgram. page break look ahead for standard architectures, the memory controller will break cycle when bus agent changes. SM731 can allow a "no wait cycle" during agent changes if the preceding and current agents are in the same page. memory timing control memory timing control is configured via md [7:0] and md [31:24] during power-on reset. they should always be set the same. see reference table 20 in the initialization section for a complete description of these memory configuration bits. note: md[32-0] has pull-up resistors on i/o pads. the default configuration is therefore a logical "1" during power-on reset. to set an md line to 0, an external pull-down resistor needs to be added. after power-on initialization, software can be used to overwrite the initial setting by writing to mcr62 - bits [7:0] correspond to md [7:0], and mcr76 - bits [7:0] correspond to md [31:24].

2d drawing engine 6 - 1 silicon motion ? , inc. SM731 confidential databook chapter 6: 2d drawing engine SM731's 128-bit drawing engine is designed to accelerate mi crosoft's directdraw and dir ect3d applications. the engine contains a 3-operand alu with 256 raster operations, source and destination fifos, as well as a host data fifo. the drawing engine pipeline allows single cycle op erations and runs at the memory clock speed. SM731's drawing engine includes several key functions to achieve the high gui performance. the device supports color expansion with packed mono font, color pattern fill, host blt, stretch blt, short stroke, line draw, and others. dedicated pathways are designed to transfer data between host interface (hif) bus and drawing engine, and memory interface (mif) bus and drawing engine. in addition, the drawing engine supports rotation biblt for any block size. this feature allows conversion between landscape and portrait disp lay without the need for special software drivers. the drawing engine offers several 3d assist features. the drawing engine supports low-resolution modes and hardware arithmetic stretching to allow 3d to be rendered to a smaller back buffer and scaled up to the front buffer. SM731 also supports fast dma blt, source clear during blt, transpar ent blt, programmable blter stride, page flip, and alpha blending bitblt.

display processors 7 - 1 silicon motion ? , inc. SM731 confidential databook chapter 7: display processors SM731 has two fully independent display processors, which mix graphics data with up to two overlaid video windows. each processor can output the combined image to a separate display device (lcdout, crt or tv). by implementing two processors (or controllers), SM731 allows for dual view/ dualmon implementations, where two independent display devices are used simultaneously, each one with its own timing, resolution and content. the primary display processor, also referred to as the pane l controller, is more complex than the secondary processor (referred to "video processor" or crt co ntroller) because its back-end is specifically designed to drive lcd panels. it has built in controls and registers that are specific for those display devices. section "flat panel registers" details the registe rs for the primary display processor while section "crt controller registers" details the registers for the secondary display processor. in order to accommodate a wider range of applications, some SM731 display in terfaces can display data from either processor, according to the diagram below. the inte rface data path is controlled by register fpr100. figure 7: display data source each display processor has it?s own lut to support index mode as well as gamma correction. the size of the ram list is 256x24. each display processor also has it?s own hardware cursor (32x32) and pop icon generator. lvds1 lvds2 digital out panel controller crt controller rgb dac tv out tv encoder display processor 1 display processor 2 lvds1 lvds2 digital out panel controller crt controller rgb dac tv out tv encoder display processor 1 display processor 2

zoom video port and video capture unit 8 - 1 silicon motion ? , inc. SM731 confidential databook chapter 8: zoom video port and video capture unit zoom video port SM731's zoom video port (zv port) is designed to interface with video solutions implemented as pcmcia (or pc cardbus) cards: examples are ntsc/pal decoders, mpeg-2 d ecoders, and jpeg codecs. the zv port can also directly interface with an ntsc/pal decoder, such as phillips 7111 or bt819. figure 8 illustrates an example of the phillips video encoder interface via the zv port. incoming video data from the zv port interface can be yuv or rgb format. the data can be interlaced or non-interlaced. the zv port can be configured for output if the video capture function is disabled. 18-bit graphics and video data in rgb format can be sent out when the zv port is configured for output mode. the zv port may also be configured as a test port. up to 20 signals from each of the logic blocks within SM731 can be brought out to an internal test bus (td bus) connected to the zv port. system designers or silicon validation engineers can access these signals by setting the test0, test1, usr0, us r1, and usr2 pins. this approach can bring out a total of 180 internal signals to the primary i/o pins. the test port capability can be used to enhance fault coverage, as well as reduce silicon validation or debugging time. table 6 lists signal definitions for the following zv port interface configurations: yuv input mode, rgb input mode, and graphics/video (output mode). figure 8: video encoder interface via video port philips saa7110/ saa7111 SM731 y [7:0] uv [7:0] href vs llc sda scl y [7:0] uv [7:0] href vref pclk sda scl video ntsc/pal rf signal
8 - 2 zoom video port and video capture unit silicon motion ? , inc. SM731 confidential databook table 6: SM731 video port interface i/o compliance note 1: blank pin can used as tvclk output, which is independent of zv port. note 2: vindex [7:0] is indexed video out note 3: smi test bus is for internal use only video capture unit the video capture unit captures incoming video data from the zv port and then stores the data into the frame buffer. the video capture unit support several features to maintain display quality, and balance the capture rate:  2-tap, 3-tap, and 4-tap horizontal filtering  2 to 1 and 4 to 1 reduction for horizontal and vertical frame size  yuv 4:2:2, yuv 4:2:2 with byte swap, rgb 5:5:5, and rgb 5:6:5  multiple frame skipping methods  interlaced data and non-interlaced data capture  single buffer and double buffer capture cropping SM731 uses the video processor block to display the captured data on the lcd, tv, or crt display. the captured data can be displayed through video window i or video window ii. the stretching, color interpolation, yuv-to-rgb conversion, and color key functions are performed in the video processor. SM731's video processor can simultaneously process captured video data and perform cd-rom playback on two independent video windows. SM731 also supports real-time video capture to the hard drive or system memory through pci master mode or slave mode. in pci bus master mode, SM731 uses the drawing engine's host blt and host dma functions to maximize performance. video port interface zv port (input mode) i/o ntsc/pal decoder (input mode) i/o graphics/video (output mode) i/o vref vs i vs i r7 o href href i href i r6 o blank (note1) (note1) blank o pclk pclk i pclk i pclk o p15 uv7 i r7 i r5 o p14 uv6 i r6 i r4 o p13 uv5 i r5 i r3 o p12 uv4 i r4 i r2 o p11 uv3 i r3 i g7 o p10 uv2 i g7 i g6 o p9 uv1 i g6 i g5 o p8 uv0 i g5 i g4 o p7 y7 i g4 i g3/vindex_[7] o p6 y6 i g3 i g2/vindex_[6] o p5 y5 i g2 i g7/vindex_[5] o p4 y4 i b7 i g6/vindex_[4] o p3 y3 i b6 i g5/vindex_[3] o p2 y2 i b5 i g4/vindex_[2] o p1 y1 i b4 i g3/vindex_[1] o p0 y0 i b3 i g2/vindex_[0] o
zoom video port and video capture unit 8 - 3 silicon motion ? , inc. SM731 confidential databook functional description SM731's video capture unit supports the video port extension (vpe) specification for video stream processing. this capture unit includes clip block, filter block, shrink block, and fifo control block. figure 9 and figure 10 illustrate the SM731 video capture block diagram and data flow. the clip functional block is used to select the desired rectangles from the video stream to be captured. vpr40 regist er (video source clipping control) is used to define the upper left corner of the rectangle from the video source. vp r44 register (video source capture size control) is used to define the height and width of the rectangle from the video source. figure 9: video capture block diagram the filter functional block controls horizontal filtering logic. cpr00 (capture port control) bit 21 and bit 20 are used to select 2 tap, 3 tap, and 4 tap filtering. the shrink functional block is used to not only reduce the storage area for both display memory and hard drive, but also increase performan ce of video capture and video playback. cpr00 bit 19 and 18 are used to enable vertical reduction, and bit 17 and bit 16 ar e used to enable horizontal reduction. with filter and shrink functions, SM731 is able to achieve high video capture performance and maintain optimal video playback quality. cpr00 bit 13 to bit 11 are use to select 8 different frame skipping options in the event the capture rate is less than the incoming video stream. cpr00 bit 10 and bit 9 are used to support interlaced capture and double buffer capture. cpr00 bit 1 and bit 2 are used as control/stat us bits for buffer i and buffer ii. the captured data can be displayed on either video window i or video window ii. the video capture driver needs to program vpr1c (or vpr30), video window i (or ii) source start address, with the same address value from capture port buffer i or ii start address register. vpr00 (miscellaneous graphics and video control) bit 24 may be used to automatically display the capture data on video window i without programming vpr1c register. this feature is independent of single buffer or double buffer mode. clip filter shrink fifo on screen graphics display memory capture buffer i capture buffer ii vpr48 vpr4c vpr1c vpr30 video window i video window ii video stream from zv port drawing engine pci bus interface block
8 - 4 zoom video port and video capture unit silicon motion ? , inc. SM731 confidential databook figure 10: video capture data flow theory of operation initialization  enable video capture (cpr00 bit 0 = 1)  preset buffer i and buffer ii status/control bits (cpr00 [2:1] = 11b)  enable drawing engine (dpr0e bit 4 = 1)  select host blt read command function (dpr0e [3:0] =9h)  enable pci bus master mode (scr17 bit 6 = 1)  select field detection, vref/href polarity, vertical/horizontal reduction, horizontal filtering, video capture input data format, frame skip, interlaced/non-interlaced and other miscellaneous settings (cpr00, capture port control register) capture data capture buffer vpr40 [25:16] vpr40 [9:0] vpr44 [26:16] vpr44 [10:0] filtering & scaling cropping f r o m v i d e o s u p p l i e r
zoom video port and video capture unit 8 - 5 silicon motion ? , inc. SM731 confidential databook table 7: bit setting summary for video capture the video capture unit supports the following types of capture modes:  single buffer mode with continuous capture  single buffer mode with conditional capture  double buffer mode with continuous capture  double buffer mode with conditional capture  interlace and non-interlaced mode a summary of each of the video capture modes follows:  single buffer mode with continuous capture ? single buffer mode with conditional capture b1s buffer 1 status/control (cpr00 bit 1) b2s buffer 2 status/control (cpr00 bit 2) continuous capture bit 8 = 0 conditional capture bit 8 = 1 single buffer bit 9 = 0 double buffer bit 9 = 1 non-interlaced mode bit 10 = 0 interlaced mode bit 10 = 1 video capture unit (vcu) drawing engine (de) video processor (vp)  continuously capture incoming video data to capture buffer 1  independent of b1s and b2s bits it is not recommended to use the drawing engine to transfer captured data from display memory to hard drive or system memory in this mode. this mode is used to view the captured data only.  vpr00 bit 24 = 0 captured data can be displayed on either video window i or video window ii by setting video window start address register.  vpr00 bit 24 = 1 captured data is automatically displayed on video window i. video capture unit (vcu) drawing engine (de) video processor (vp) a) vcu monitors b1s bit b) if b1s = 1, start capture c) vcu will reset b1s to 0 after it completes a frame d) go to step ?a? a) test b) if b1s = 0, sw will activate the de to transfer captured data from capture buffer 1 to hard drive or system memory c) de will set b1s bit to 1 after it completes a frame d) go to step "a?  vpr00 bit 24 = 0  captured data can be displayed on either video window i or video window ii by setting video window start address register.  vpr00 bit 24 = 1  captured data is automatically displayed on video window i
8 - 6 zoom video port and video capture unit silicon motion ? , inc. SM731 confidential databook  double buffer mode with continuous capture  double buffer mode with conditional capture  interlaced capture cpr00 bits 10 are used to select the in terlaced capture mode. in most of vide o capture applications, an interlaced video stream will be treated as non-interlaced video stream by dropping all even frames (cpr00[13:11] = 010b), or dropping all odd frames (cpr00[13:11] = 011). this approach will reduce artifacts when playing back the captured data. however, in some video capture applications, de-interlacing is n eeded to handle the incoming interlaced video stream. for the de-interlacing case, cpr00 bit 10 needs to be set to 1 to enable interlaced capture for incoming interlaced video stream. the double buffer mode (cpr00 bit 9 = 1) needs to be turned on at the same time. capture buffer 1 and capture buffer 2 are combined together as a single buffer with one line offset. figure 11 illustrates the capture buffer structure. the video capture driver will preset b1s and b2s bits to 1 to initialize the buffer 1 and 2 status/control bits. the video capture unit will start video capture if any one of b1s and b2s = 1. after vcu fills capture buffer 1 and 2, both b1s and b2s bits are set to "0" by vcu. the video capture driver will activate drawing engine to transfer captured data in capture buffer 1 and 2 to system memory or hard drive when both b1 s and b2s are "0". after the co mpletion of the transfer, the drawing engine will set both b1s and b2s to "1". the video capture unit then continues video capture and repeats the same protocol. during video playback, the captured data can be displayed on either video window i or video window ii. it is not recommended to display both even frame and odd frame for video playback. the video captured driver can program video window i (or ii) source start address register and video window i (or ii) source width and offset register in such a way that odd frame (or even frame) captured data will be dropped during video playback. the scaling, color interpolation, and yuv-to-rgb conversion functions can also be enabled at the same time. video capture unit (vcu) drawing engine (de) video processor (vp)  continuously capture the incoming video data into capture buffer 1 or buffer 2  automatically switch from one buffer to the other when vcu completes a frame  independent of b1s and b2s bits it is not recommended to use de to transfer captured data from display memory to hard drive or system memory in this mode. this mode is used to view the captured data only.  vpr00 bit 24 = 0 captured data can be displayed on either video window i or video window ii by setting video window start address register.  vpr00 bit 24 = 1 captured data is automatically displayed on video window i. if capture buffer 1 is used by vcu, video window i will display captured data from capture buffer 2 video capture unit (vcu) drawing engine (de) video processor (vp) a) vcu monitors b1s and b2s bits b) if b1s (or b2s) = 1, start video capture and store into capture buffer 1 (or buffer 2). c) vcu will reset b1s (or b2s) to 0 after it completes a frame d) vcu will continue video capture if b1s or b2s = 1 e) go to step "a" if both bits = 0 a) sw monitors b1s or b2s bit b) if b1s (or b2s) = 0, sw will activate the de to transfer captured data from capture buffer 1(or buffer 2) to hard drive or system memory c) de will set b1s (or b2s) bit to 1 after it completes a frame d) de will continuously transfer e) data from capture buffer 1 or 2 if b1s or b2s = 0 f) go to step "a " if both bits = 1  vpr00 bit 24 = 0 captured data can be displayed on either video window i or video window ii by setting video window start address register.  vpr00 bit 24 = 1 captured data is automatically displayed on video window i. if capture buffer 2 is used by vcu, video window i will display captured data from capture buffer 1.
zoom video port and video capture unit 8 - 7 silicon motion ? , inc. SM731 confidential databook figure 11: capture buffer structure in interlaced mode even field odd field even field even field odd field even field capture buffer 2 to drawing engine or video processor capture buffer 1 from video capture unit

flat panel interface 9 - 1 silicon motion ? , inc. SM731 confidential databook chapter 9: flat panel interface the SM731 can directly drive lcd panels equipped with cm os digital interface and/or panels with lvds interface. there are two independent display controllers inside SM731 : the panel controller also referenced as the primary controller and the crt controller also referred to as the sec ondary controller. because of this, SM731 is able to drive two screens with different images, from separate frame buffers and at independently programmable timing and resolution. furthermore, the lcd panels can be programmed to display images from either controller, with some restrictions. see section display processors. the digital interface can drive data from either the panel controller or the crt co ntroller, just like the lvds2 interface. the lvds1 interface is hardwired to drive data from the panel controller (primary display). if the digital interface and lvds2 interface are both turned on to drive the single pixel pa nels, their data source has to be the same either from the panel controller or crt controller. there will be no restriction if only one interface is on for single pixel panel or lvds2 is used for double pixel panel. digital interface the digital interface is 24 bit wide and can be programmed to drive 24 bpp or 18bpp displays. the image source, along with the corresponding control signals (syncs, shift clock an d power control), is selectable between the primary (fp) or secondary (crt) controllers through control bit fpr100[5]. fpr100[5] = 1, interface drives data and control signals from panel controller (primary). fpr100[5] = 0, interface drives data and control signals from crt controller (secondary). table 8: digital interface pinout digital interface pinout fdata [23:0] flat panel data bits 23 to 0 for direct connection to 18 or 24 bbp panel or to external tmds transceiver. these lines can be programmed to convey information from the panel controller (primary display source) or the crt controller (secondary display source). single pixel per clock mode support only. fdata[23:22], fdata[15:14] and fdata[7:6] are driven low if panel type is set to 18 bpp. fphsync horizontal sync signal from panel controller (primary display source) or crt controller (secondary source). fpvsync vertical sync signal from panel controller (primary display source) or crt controller (secondary source). de1 display enable signal from panel controller (primary display source) or crt controller (secondary source). this signal is used to indicate the active horizontal display time. fpsclk flat panel shift clock. this is the pixel clock for flat panel data. fpen2 flat panel enable. this signal needs to become active after all panel voltages, clocks, and data are stable. this signal also needs to become inactive before any panel voltages or control signals are removed. fpen is part of the vesa fpdi-1b specification. panel controller or crt controller can be timing source. fpvdden2 flat panel vdd enable. this signal is used to control lcd panel power. panel controller or crt controller can be timing source.
9 - 2 flat panel interface silicon motion ? , inc. SM731 confidential databook table 9: fpdata definition lvds interfaces the lvds interfaces can be used to drive two independent pa nels, one displaying data from the primary controller and the other displaying data from the secondary controller. they can also be combined to drive a single, two pixels per clock, high resolution panel. each lvds block compresses 24 bits of rgb data and 4 bits of lcd timing into four differential fpvbiasen2 flat panel voltage bias enable. this signal is used to control lcd bias power. panel controller or crt controller can be timing source. fpdata definition pin 18bpp, single pix/clk panel 24bpp, single pix/clk panel fpdata23 drive low r7 msb fpdata22 drive low r6 fpdata21 r5 msb r5 fpdata20 r4 r4 fpdata19 r3 r3 fpdata18 r2 r2 fpdata17 r1 r1 fpdata16 r0 lsb r0 lsb fpdata15 drive low g7 msb fpdata14 drive low g6 fpdata13 g5 msb g5 fpdata12 g4 g4 fpdata11 g3 g3 fpdata10 g2 g2 fpdata9 g1 g1 fpdata8 g0 lsb g0 lsb fpdata7 drive low b7 msb fpdata6 drive low b6 fpdata5 b5 msb b5 fpdata4 b4 b4 fpdata3 b3 b3 fpdata2 b2 b2 fpdata1 b1 b1 fpdata0 b0 lsb b0 lsb digital interface pinout
flat panel interface 9 - 3 silicon motion ? , inc. SM731 confidential databook wire pairs, up to 392 mbytes per second at a maximum clock rate of 112 mhz. a fifth differential pair transmits the interface clock. this way, each lvds block ca n drive one sxga+ panel (1400x1050x24 @60hz). the lvds1 interface is hardwired to panel controller (primary). it can be programmed to drive 18 or 24 bpp panels, and, if used in conjunction with the lvds2 interface, it can be used to drive a two channel, two pixels per clock panel of up to qxga size (2048x1536). associated with the lvds1 interface are the following cont rol signals, whose timing source is always the primary controller: fpen1, fpvdden1 and fpvbiasen1.

miscellaneous functions 10 - 1 silicon motion ? , inc. SM731 confidential databook chapter 10: miscellaneous functions this chapter describes functions of SM731 such as the video rom bios interface, vesa dpms, and i 2 c / vesa ddc2b. video bios rom interface the video bios contains code for chip power-on initialization, graphics mode setup, and various read/write routines to the frame buffer. the video bios can be burned into a sepa rate video bios eprom (this is the typical case for add-in cards) or be integrated into the system bios rom (this is the typical case for a motherboard graphics implementation). to support separate video bios rom access, bios address decode must be enabled by setting csr30 (expansion rom enable base address register) bit 0 = 1. for implementations where video bios is integrated into the system bios rom, bios address decode access must be disabled by clearing csr30 bit 0. figure 12 shows the external video bios rom configuration interface for SM731. the ~romen (rom enable) signal from SM731 connects to the oe and ce signals of the bios rom. since video bios rom address and data are shared with the video memory data (md) lines, programmers must ensure that the memory bus is inactive when reading from the video bios rom. for this case, the video bios rom must be read out and shadowed (typically in system memory at c0000) immediately after reset. direct physical access to the video bios must th en be disabled to prevent interference with ensuing graphics operations. figure 12: video bios rom configuration interface SM731 bios rom md [7:0] md [47:32] ~romen d [7:0] a [15:0] ~oe ~ce 64kx8
10 - 2 miscellaneous functions silicon motion ? , inc. SM731 confidential databook vesa dpms interface SM731 supports the vesa display power management signaling (dpms) via direct programming pdr22 (lcd panel control select register) bits 5, 4, or through implementation of the chip's power down states. table 10 shows the vesa dpms states and methods for ente ring each of the dpms states. table 10: dpms summary i 2 c bus or vesa ddc2b interface SM731 provides dual ports for i 2 c-bus through usr [3:0] i/o pins for various applications such as vesa?s ddc2b monitor interface. it is recommended to use usr1 and us r0 as the primary port for sda and scl signals on i 2 c bus. usr3 and usr2 are reserved as a secondary port. gpr72 (u ser defined register 1) and gpr73 (user defined register 2) are defined to support i 2 c/ddc2 bus protocol. SM731, as an i 2 c master controller only, is designed to initiate a transfer, generate clock signal, and terminate a transfer to a slave i 2 c component. SM731's i 2 c-bus interface is designed to interface with ntsc/pal decoders, eeproms, audio decoders, and others. the operation voltage of usr [3:0] i/o pins is controlled by vpvdd, which can be configured as 5v or 3.3v. each of the usr [3:0] i/o pins has an internal pull-up resistor. to enable the data (sda) and the clock (scl) from SM731's primary port, bit 5 and bit 4 of gpr72 (3c5h index 72h) must be set as "11". to drive a logic "0" to sda line (usr1) and scl line (usr0), program gpr72 bit 1 and bit 0 to "0". the sda and scl can be read back from bit 3 and bit 2 of gpr72. figure 13 shows the basic i 2 c-bus protocol of SM731 as a master transmitter. dpms state hsync state vsync state rgb state direct programming method power down state method on pulses pulses active pdr22 [5:4] = 00 - standby no pulses pulses blank pdr22 [5:4] = 01 automatic standby dpms state when enter standby mode suspend pulses no pulses blank pdr22 [5:4] = 10 ccr69[2]=0 selects suspend dpms state when in sleep mode off no pulses no pulses blank pdr22 [5:4] = 11 ccr69[2]=1 selects off dpms state when in sleep mode
miscellaneous functions 10 - 3 silicon motion ? , inc. SM731 confidential databook figure 13: SM731 i 2 c bus protocol flow chart linear to tile address conversion for cpu access in order to access the frame buffer in tile mode during the time application (software has no idea about the tile format in the memory), internal hardware has to make the address conversion to address to the right tile location. for additional information see chapter 24: video capture control registers. bus busy? initiate start send 7-bit slave address with r/~w bit ack from slave? time out? send 2nd byte slave address abort transfer ack from slave? time out? send one byte slave address ack from slave? time out? last byte? stop transfer yes no no check gpr72 [3:2] = 11 yes, = 11 yes no abort transfer yes no no yes yes no yes yes no abort transfer yes check gpr72[3] = 0 check gpr72[3] = 0 check gpr72[3] = 0 optional no

clock synthesizers 11 - 1 silicon motion ? , inc. SM731 confidential databook chapter 11: clock synthesizers SM731 integrates three programmable clock synthesizers for memory clock (mclk), video clock 1 (vclk), and video clock 2(vclk2). vclk1 is utilized for standard crt only, lcd only, or crt/lcd display modes for which the refresh rate for both devices is the same. vclk2 may be utilized when virtual refresh mode is implemented - for this case, vclk1 is utilized for panel timing and to clock the panel display block within SM731. vclk2 may be utilized to clock the crt interface independently for lcd/crt display modes or to independently clock various functional blocks within the device to save power under lcd only display mode. please see the virtual refresh discussion under the power management section for additional details regarding power saving capabilities under virtual refresh architecture. figure 14 illustrates the control logic for mclk, vclk, vclk2. the figure also shows the clock generator module for wfifo (wfifoclk), rfifo (rfifoclk), ram (ramclk), video capture (vcmclk), drawing engine (dpmclk), and video processor (vpclk). tvclk is used fo r an external analog tv encoder (this clock is either derived from 14.318mhz base clock - ntsc, or from separate 17.734480mhz clock source connected to input signal palclk - pal). figure 14: clocks generator block diagram the vclk pll is programmed using the vclk numerator register (vnr), ccr6c, and vclk denominator (vdr) and post scalar (ps) register, ccr6d. the vclk frequency is based on the following equation: ~excken ccr68_6 ccr68_7 ckin pll1 1 0 1/4 1/8 1/16 pd20_4 pd20_5 0 1 2 3 s1 s0 vclk mckin pll2 1/4 1/8 1/16 mclk ~excken 0 1 2 3 s1 s0 0 1 0 1 2 3 s1 s0 0 1 1/2 vclk mclk vclk2 vclk fpr31_7 ccr69_0 ccr69_1 vrclk clock generator vclk mclk pdr21[5:0] standby sleep auto_off wfifoclk rfifoclk ramclk vcmclk dpmclk vpclk tvclk sleep standby vclk2 ckin pll3 1 0 1/4 1/8 1/16 0 1 2 3 s1 s0 vclk2
11 - 2 clock synthesizers silicon motion ? , inc. SM731 confidential databook the post scalar is used to support vclk frequencies whic h need a large vdr number. with ps enabled, the vdr number can be set to ? of the original vdr number. this helps to reduce jitter and maintain accuracy. the vclk2 pll is programmed using the vclk2 numerator register (vclk2nr), ccr6e, and vclk denominator (vclk2dr) register ccr6f. the vclk2 frequency is based on the following equation: table 11: recommended vnr and vdr values for common vclk settings notes: 1. vnr and vdr numbers are hard coded in vga modes. 2. post scalar enabled. resolution mode ref. rate vclk (mhz) vnr vdr 640x480 60hz 25mhz 07h 82h 640x480 75hz 31mhz 16h 85h 640x480 85hz 36mhz 88h 9bh 800x600 60hz 40mhz 27h 87h 800x600 75hz 49mhz 4ch 8bh 800x600 85hz 56mhz 37h 87h 1024x768 60hz 65mhz 29h 09h 1024x768 75hz 78mhz 0bh 02h 1024x768 85hz 94.5mhz 21h 05h 1280x1024 60hz 104mhz 53h 0bh 1280x1024 75hz 134mhz 2fh 45h 1280x1024 85hz 157mhz 16h 42h 1400x1050 60hz 122mhz 4dh 09h 1400x1050 75hz 149mhz 49h 1eh 1400x1050 85hz 181mhz 65h 08h 1600x1200 60hz 161mhz 22h 43h 1600x1200 75hz 202mhz 8dh 4ah 1600x1200 85hz 229mhz a0h 4ah vclk = 14.31818 mhz vnr vdr 1 + 1ps vclk2 = 14.31818 mhz ? vclk2nr vclk2dr
clock synthesizers 11 - 3 silicon motion ? , inc. SM731 confidential databook the mclk pll is programmed using the mclk numerator register (mnr), ccr6a, and mclk denominator register (mdr), ccr6b. mclk frequency is based on the following equation: mclk = 14.31818 mhz mnr mdr

power management 12 - 1 silicon motion ? , inc. SM731 confidential databook chapter 12: power management the SM731 supports three type of power management:  acpi - acpi requirements as defined in the pci bus management interface specification 1.0 (ppmi v1.0) and display device class power management specification v1.0a.  dynamic power management control - silicon motion?s proprietary and pattern pending scheme to control the clock rate under different operational modes. the contro l mechanism provides contro l to the external voltage regulator to achieve power saving under normal operations.  deep sleep - all pll and pads are turned off. acpi the SM731 supports d0-d3 modes of operation via the software programming of the power management control/status register pmscr[1:0]. as required by the pci bus mana gement interface specification; the pci configuration space status register (offset 06h) bit 4 is set to "1" to indicate new capabilities have been defined for SM731. at offset 34h, the cap_ptr register, stores the offset of the new capabilities (this register is hardwired to 40h). the first byte at offset 40h h as a value of 01h, which indicates a power management capability (supports d1 and d2 states in addition to the required d0 and d3 power states). the second byte has a value of 00h indicating the no additional new capability features. (note: SM731 does not offer support for optional ~pme capabilities as defined in ppmi v1.0. please refer to the pci bus power management interface specification 1.0 and display device cl ass power management reference specification v1.0a for additional details). the scr24_[0] has to be set to 1 to enable the acpi function. in acpi the d1 state (stand by mode), most clocks are shut down to only maintain the minimum operational modes such as screen refresh. in acpi d2 and d3 states (suspend and sleep modes), all clocks are shut down. the dram enters th e self refresh mode, and pdr20_[7] need to be set to 1 to enable these states. display driver support for acpi under windows 98 and future versions of windows nt will be provided by silicon motion in accordance with pc97 and pc98 requirements. the crt power management is controlled by the acpi states according to the standards. the lcd power management and power sequencing are controlled by fpen, fpvdd, and vbias control pins. please refer to the flat panel register fpr100 for details. acpi mode sequence  set pdr24_[0] = 1 (acpi enable)  set pdr20_[7]=1 (enable sleep mode)  set pdr20_[6] = 1 (self dram refresh)  set scr25_[1] = 1 to power down agp4xpll.  set pdr21_[4] = 1 shut off crt pixel shift clock  pdr20_[1] = 1 turn off lcd panel data pains  fpr100_[13:12] = 00 power off lvds 1 and 2 module  clock divider set up
12 - 2 power management silicon motion ? , inc. SM731 confidential databook pdr20_[5:4] = 11 - enable clock divider in sleep mode ccr9e_[7:0] = 3f - memory clock no divide, all other clocks divide 16  activate acpi mode table 12: interface signals sleep mode states signal name sleep mode host interface ad [31:0] tri-state c/ ~be [3:0] tri-state par tri-state ~frame tri-state ~trdy tri-state ~irdy tri-state ~stop tri-state ~devsel tri-state idsel x clk x ~rst h ~req tri-state ~gnt x ~inta tri-state power down interface ~pdown l ~clkrun open-collector clock interface refclk/palclk x ckin x lvdsclk tri-state ~excken h memory interface ma [11:0] h md [63:0] h or l (note 2) ~we h ~ras l ~cas l ~cs [1:0] l ~dqm [7:0] h dsf l ba h
power management 12 - 3 silicon motion ? , inc. SM731 confidential databook sdcken l (self-refresh), h (cas-b-ras) sck depends on pll ~romen h flat panel interface fdata [23:0] l fpsclk l fpen l fpvdden l vbiasen l lp/fhsync l fp/fvsync l crt interface r, g, b 0 v crtvsync l crthsync l video port interface p [15:0] l pclk h vref h href h blank/tvclk h general purpose registers/i 2 c usr3 h usr2 h usr1/sda h usr0/scl h test mode pins test [1:0] l signal name sleep mode
12 - 4 power management silicon motion ? , inc. SM731 confidential databook table 13: gated clock trees dynamic power management control (dpmc) the dpmc is different from the acpi power-down mode, and can be used to minimize power usage under normal operation without going to "sleep" mode. all the major functional blocks have their own gated clock tree which can be shut down independently via software control. the dpmc can also dynamically control the engine clock and memory clock rate to achieve power savings, and the clock rate adjustment is controlled by a look up table (register ccr94 - ccr9d). depending on the state of the dpmc, the clock rate can be adjusted automatically. the dpmc has three states normal, save, and idle. these states depend on the ac power on/off, bus activity, and 3d engine on/off. to enable the dynamic power management control pdr23_[7] 0 = disable dpmc 1 = enable dpmc dpmc interrupt the "acon" pin is a system provided input status control signal. 0 = "acon" means the ac power is off. saving battery (dc power) becomes important. 1 = "acon" means the ac power is on. once the dpmc is enabled(pdr23_[7]=1) the SM731 can generate an interrupt by monitoring the acon pin. when the acon input pin status changes from 0->1 or from 1->0 the interrupt will be software generated to control the dpmc. clock tree name control register (1=disable unless noted) sleep standby video capture pdr21_[2] off off crt video pdr21_[0] off off lcd video pdr21_[4] off off lcd wfifo pdr21_[5] off off 2d engine pdr21_[1] off no effect motion comp ccr66_[1] off off 3d engine ccr66_[0] off off crt dac pdr21_[7] off off crt clut ccr66_[6] off off lcd clut ccr6_[7] off off tv encoder ccr65_[5](1=enable) off off tv yc dac ccr65_[6](1=enable) off off tv svhs dac ccr65_[7](1=enable) off off crt pix.shift clk pdr21_[3] no effect no effect pll pwrdown enb pdr21_[6] no effect no effect
power management 12 - 5 silicon motion ? , inc. SM731 confidential databook dpmc interrupt control register bits scr1c_[1] - dpmc interrupt status bit scr1f_[5] - dpmc interrupt enable bit 0 = disable dpmc interrupt 1 = enable dpmc interrupt scr1f_[1] - dpmc interrupt mask bit: 0 = no interrupt mask 1 = mask out dpmc interrupt dpmc states once the dpmc is enabled, there are 3 states: normal state: if "acon" status pin is 1, dpmc will stay (ac power on) in "normal" state. dpmc will always stay in this state if pdr23_[7] = 0. the engine clock rate is determined by: ccr6a/ccr6b if 3d engine is off (ccr6a - ccr98)/ccr6b if 3d engine is on the memory clock rate is determined by: ccr63/ccr64 if 3d is off (ccr63 - ccr99)/ccr64 if 3d is on powersave state: if "activity detection" detect no bus (ac power off) activities, dpmc will go to ?poweridle" state. otherwise the dpmc will stay in "powersave" state. the engine clock rate is determined by: (ccr6a - ccr94)/ccr6b if 3d engine is off (ccr6a - ccr9a)/ccr6b if 3d engine is on the memory clock rate is determined by: (ccr63 - ccr95)/ccr64 if 3d is off (ccr63 - ccr9b)/ccr64 if 3d is on poweridle state: if "activity detection" detected bus (bus idle) activity dpmc return to "powersave" state. otherwise stay in "poweridle" state. the engine clock rate is determined by: (ccr6a - ccr96)/ccr6b if 3d engine is off (ccr6a - ccr9c)/ccr6b if 3d engine is on the memory clock rate is determined by: (ccr63 - ccr97)/ccr64 if 3d is off (ccr63 - ccr9d)/ccr64 if 3d is on
12 - 6 power management silicon motion ? , inc. SM731 confidential databook SM731 has control logic to monitor the host bus activities. the dpmc can be programmed to define how long it takes to wake up from idle states and what kind of bus activity detection should be monitored by dpmc for wake up as the following. pdr23_[6:5] 00 = detect memory write/read & io write/read and capture enable 01 = detect memory write & io write and capture enable 10 = detect memory write/read and capture enable 11 = detect io write/read and capture enable pdr23_[3:0] - timer control to count number of vsync (crt timing). if there is no bus activities in a specified period, the power management will enter "idle" mode. 0000 = disable activity detection 0001 = 64 vsync 0010 = 128 vsync 0011 = 256 vsync 0100 = 512 vsync 0101 = 1k vsync 0110 = 2k vsync 0111 = 4k vsync 1000 = 8k vsync 1001 = 16k vsync 1010 = 32k vsync 1011 = 64k vsync 1100 = 128k vsync 1101 = 192k vsync 1110 = 256k vsync 1111 = 384k vsync activity output pin (p22) there is an activity output pin which can be used to control an external power re gulator to adjust the core vdd to achieve power savings. scr18_[7] 0 = select ~clkrun as input for pin p22. there is no ac tivity output for this case. this mode is considered an alternative to implementing reduceon. if the activity pin is not available, see the appropriate app note for further details). 1 = select activity as output for pin p22. this activity pin will always be low if ?acon? input pin is high; otherwise, the output will be controlled by ccr65_[4]: 0 = output low status 1 = output high status note: the silicon motion software implements this pin as reduceon control pin which will control the external vdd power regulator. if the activity is low, then the vdd will be 2.5v. if activity is high, then the vdd will be dropped. deep sleep mode
power management 12 - 7 silicon motion ? , inc. SM731 confidential databook after the SM731 acpi mode is activated, the "deep sleep mode" can be used to fu rther reduce the static current of the chip by shutting down all the internal plls and all agp/pci pads. the sequence of entering this mode should be: acpi => deep sleep mode. before exiting from the acpi mode, the "deep sleep mode" must first be disengaged. to enter this mode, pull the "pwdown" pin to low (normally the pin is high by the internal pull up). pdr21_[6] = 1 has to be set to 1, before the pull pwdown pin to low.

motion compensation specification 13 - 1 silicon motion ? , inc. SM731 confidential databook chapter 13: motion compensation specification overview the motion compensation block (mc) executes a series of instructions in a pipelined fashion. there is actually only one type of instruction with several flags that control the instruction execution. the mc instruction is similar to a cpu arithmetic instruction with three sources (imm - immediat e operand, mrd - memory read and acc - accumulator) and one destination (mwr - memory write). the main difference between standard cpu instructions and those used by the mc is that the mc instruction works on rectangular blocks of data instead of 8, 16, 32, or 64-bit integers. the rectangular blocks of data (rectangles) used by the mc are 2-dimensional arrays containing 8-bit values. for the current implementation, the horizontal a nd vertical sizes (hsize and vsize) are limited to the following ranges: hsize = 8 or 16; vsize = 4 or 8. the mc requires one 128x16 sram for temporary storage of the input and output array values. it acts as a cpu accumulator. the throughput of the mc pipeline is two pixels per cycl e. under worst case assumptions a mpeg-2 mp@ml picture will thus require 22 mcycles/second. data flow and external system responsibilities all instructions for motion compensation are generated by a software front-end and fed to the graphics controller via a standard software api. the instructions specify two differ ent types of operations: (1) memory accesses used for reading prediction data and writing reconstructed pels, and (2) data processing operations used to combine predictions with the error terms generated by the idct operation. the mc core handles all data processing operations required for motion compensation. the graphics memory controller handles the memory access operations. the memory controller must read the instructions generated by software, fetch prediction data, feed the data to the mc block and write the final reconstructed pels into the proper location. mc top level architecture the top level architecture of the mc core is shown in figure 15. it consists of a simplified quadrilinear filer (mc_qlf - this is the data path), a 128x16 dual port sram, and a controller (mc_ctl). the mc has four data busses: command (cmd), immediate operand (imm), memory read (mrd) and memory write (mwr).
13 - 2 motion compensation specification silicon motion ? , inc. SM731 confidential databook figure 15: mc top level architecture in the current architecture all input and output busses are kept separate to offer the maximum processing throughput. except for the command bus, all busses can operate continuously at one 16-bit or 18-bit value per cycle (two pixels/cycle). all busses use a rdy-ack protocol and can be stalled on any cycle. for mpeg the idct output is fed through the imm bus and the prediction through the mrd bus. for bidirectionally interpolated macroblocks, first the forward prediction is read, half-pel interpolated, an d stored in the 128x16 memory (block accumulator). next, the backward prediction is read, half-pel interpol ated, and added to both the acc (forward prediction) and imm (immediate or idct) data. figure 16: control block diagram words from the cmd bus are loaded direct ly into the 16-bit cmd register as the command pipeline advances. the flags0 and flags1 registers each hold exactly one instruction each and together form a 2 instru ction fifo. one instruction is encoded as 2 or more 16-bit words, which means that it will ta ke 2 or more pipeline advances before a flags register has accepted an entire instruction. having 2 instructions queued at a time allows the mc to prep are an idle qlf pipeline with data ahead of time - before the current instruction has completed. mc_ctl mc_qlf sram 128x16 motion compensation commands cmd idct data prediction data (from memory) imm mrd acc mwr to memory motion compensation commands demux cmd flags 0 cmd flags 1 cmd reg
motion compensation specification 13 - 3 silicon motion ? , inc. SM731 confidential databook figure 17: qlf block diagram the quadrilinear filter consists of three pipelines, namely the acc, mrd, imm pipelines. the acc pipeline is not shown in block diagram because it consists of two stages external to the mc. the first stage is the synchronous sram read port while the second stage is a register that accepts sram read data. the width of th is register matches the width of the reconstruction memory write back (mwr) data and is application dependent. the mrd pipeline accepts prediction data fro m memory in a 16-bit wide format (2-pels). pel alignment, horizontal half pel interpolation, and vertical half pel interpolation are handled in the pipeline. the imm pipeline accepts idct data in a 18 -bit (9-bit pel) or 16-bit (8-bit pel) format. the data is reformatted based on the flags in the current instruction. data from the three pipelines is combined and held in the reconstruction register. the data is added together, then saturated to values between 0 and 255. from this register the data is written to the local sram 16-bits (2 pels) at a time. mc instruction format and operation figure 19 shows the mc instruction format. the flags and parame ters in the instructions are summarized in table 14. all mc commands have the most significant bit (msb) of word a set=1. commands that have the msb cleared=0, are intended for the memory controller or other control logic external to the mc. currently, the only command with msb=0 is used to indicate the end of stream: prediction data (from memory) recon reg mrd pipeline imm pipeline sram read data sram write data idct data
13 - 4 motion compensation specification silicon motion ? , inc. SM731 confidential databook figure 18: end stream instruction this end stream command can occur anywhere in a command stream and should trigger an end to the command stream transfer. after this instruction is encountered by hardware, communication would then take place between hardware and the driver to determine what step to take next. this command is intended for logic external to the mc but should also be passed on to the mc. the mc will see it as a flush command and is required in order for the results from the last valid command to be written to memory. the following table defines the format for mc instructions. notice that the msb of word a is set=1, indicating that this is an mc instruction. figure 19: mc instruction format table 14: instruction flags and parameters fedcba9876543210 a0000000000000000 b 0 0 10000 0 0 0 00000 0 f e d c b a 9 8 7 6 5 43210 a 1 - isl im8 mrd imm acc mwr thb lhb ih0 ih1 tvb lvb iv0 iv1 b - - hsize [4:0] hhp - - vsize [4:0] vhp c mrd_slot[1:0] mrd_plane[1:0] mrd_hadder [11:0] d - rvs mrd_hadder [11:0] e mrd_slot[1:0] mrd_plane[1:0] mrd_hadder [11:0] f - wvs mrd_hadder [11:0] flag parameter meaning isl immediate shift left vs. sign extend left im8 immediate data 8-bits per pixel mrd memory read imm immediate acc accumulate mwr memory write thb two horizontal blocks lhb interleaved horizontal blocks ih0 immediate operand for horizontal block 0 ih1 immediate operand for horizontal block 1 tvb two vertical blocks lvb interleaved vertical blocks iv0 immediate operand for vertical block 0 iv1 immediate operand for vertical block 1 hsize [4:0] horizontal size hhp horizontal half pel interpolation
motion compensation specification 13 - 5 silicon motion ? , inc. SM731 confidential databook each mc instruction consists of two, four or six 16-bit words. the first instruction, instruction a in figure 19, contains the instruction flags. the second instruc tion contains the rectangle size. depending on the flags in the first instruction, the remaining four instructions may or may not be present. in instruction a, the most important flags are mrd, i mm, acc, and mwr. these flags indicate what source operands are used and if the result should be stored to memory or to the accumulator (the 128x16 memory). all or none of these four flags can be set. if none of the source flags are set, the mc generates a rectangle of zeros. if the mrd (memory read) flag is set, instructions c and d must be present. these instructions specify the address from which prediction data should be fetched. the memory slot (prediction slot) from which to read the data is given by the mrd_slot [1:0]. a slot contains one frame of video which can be broken down into two or three color planes: (y, cb, cr) or (y, cb/cr interleaved). each color plane can be broken down into two fields. the top field is located in the even lines while the bottom field is located in the odd lines of the frame. the x-y offset in the slot (frame) from which to fetch the data is given by the mrd_haddr [11:0} and mrd_vaddr [11:0]. the vertical step, mrd_vstep, indicates whether every line or every other line should be read from the slot. for frame pr ediction every line is read (mrd_vstep = 0) and for field prediction every other line is read (mrd_vstep = 1). the firs t line of a rectangle of prediction data is indicated by mrd_vaddr [11:0]. in field prediction (mrd_vstep = 1), which field the data must come from depends on the location the first line of the prediction rectangle. if that line is in the top field, then the data comes from the top field. otherwise it comes from the bottom field. the parameter mrd_plane (memory read plane) indicates which video plane is being processed (0=y, 1=cb, 2=cr, 3=cbcr). for mpeg decompression the memory read plane, mrd_plane [1:0] and memorywrite plane, mwr_plane [1:0], are always equal. (note: they are provided as different values to offer increased flexibility for other applications (read from one plane and write to a different plane). if the mwr is set, instruction e and f must be present. thes e instructions specify the addr ess to which the final computed pels should be written. similar to the data read instructions, the write slot is indicated by mwr_slot [1:0]. the x-y offset is indicated by mwr_haddr [11:0] and mdr_vaddr [11:0]. the mw r_vstep bit specifies whether or not to skip a line between successive rows written in the same way that the mrd_vstep does for the prediction data. in mpeg-2 decode, mwr_vstep setting reflects the motion type for the macroblock being processed. vsize [4:0] vertical size vhp vertical half pel interpolation mrd_slot [1:0] memory read slot mrd_plane [1:0] memory read plane mrd_haddr [11:0] memory read horizontal address mrd_vaddr [11:0] memory read vertical address rvs mrd_vstep memory read vertical step mwr_slot [1:0] memory write slot mwr_plane [1:0] memory write plane mwr_haddr [11:0] memory write horizontal address mwr_vaddr [11:0] memory write vertical address rvs mwr_vstep memory read vertical step flag parameter meaning
13 - 6 motion compensation specification silicon motion ? , inc. SM731 confidential databook in instruction b, if hhp is set, horizontal half pel interpolation is performed and the mrd horizontal size shall be hsize pixels plus one. if vhp is set, vertical half pel interpolation is performed and mrd vertical size shall be vsize rows plus one. if the acc flag is set, the mc adds the content of the accumulator (the 128x16 memory to be memory read data (if present). if the imm flag is set, the mc adds the immediate data, supp lied on the imm bus, to the interpolated data, (mrd = acc)/2. the immediate data is the error term calculated by the idct. all the other nine flags have a meaning only if imm is set. im8 indicates if the immediate data is only 8 bits wide. if im8=0 the mc will accept idct data in a 9-bit per pixel format. mpeg-2 defines a range for idct data from -256 to =255 which is covered by a 9-bit two?s complement number. a setting of im8=1 indicates that the data is in an 8-bit per pixel format which approximates the full range. the isl flag is used in conjunction with im8 and differentiates between two 8-bit modes. isl is ignored when im8=0. 8-bit approximations allow data to be packed more efficiently into standard word widths. at issue is the sign bit. intra-coded macroblocks never use the sign bit since values are restricted to the range of 0 to +255, while predicted to bidirectional idct values take the range of -256 to +255. for this reason, commands are separated into two different categories: intra- coded and non intra-coded. if im8=1 and isl=0, the mc first determines the type of command currently being executed, then generates the sign bit based on the category. intra-coded values are zero extended, wh ile non intra-coded values are sign extended to the full 9 bits. software that decodes the idct data must remove the sign bit in the intra-coded case while saturating the lower 7 bits and removing the 8th bit in the non intra-coded case. non-intra coded data retains its sign bit since the saturation process results in a 8-bit twos complement number whose most significant bit represents its sign. the im8=1/isl=0 setting will put an upper limit on the amount of correction that can be made to prediction data though. after the correction idct error terms can be no greater than =127 and no less than -128. as mentioned before, mpeg-2 specifies the range to be between +255 and -256. under normal conditions values rarely exceed the smaller range since motion is relatively slow from picture to picture. when they do, it will be almost impossible for an observer to notice since the corrupted pels will be located in an area where a great deal of motion is occurring. in some rare cases though this range clipping can cause visible artifacts. they can be correct ed though, with a second imm data ?pass?. instructions with settings of mrd=1, acc=1 and imm=1 calculate results as follows: acc = (mrd+acc) / 2 = imm instructions with settings of mrd=0, acc=1 and imm=1 calculate results differently: acc = acc + imm this allows for a correction of imm data terms that were saturated to the range of [-128, +127]. the first imm pass would correct to this smaller range while the second pass would a llow for a correction to a range of [-256 +254]. to reach a correction of +255, a third pass can be generated but would not be required very often. if im8=1 and isl=1, the mc shifts the 8-bit imm data left one bit before performing calculations with it. intra coded an non-intra coded commands both treat the imm data this way. software must drop the least significant bit of the original 9- bit terms to convert to the format of the data required in this mode. this is the fastest way to generate 8-bit imm data but will result in lower quality video. images that contain large areas of a single color will suffer contour lines. the remaining eight flags are needed to accommodate all pos sible combinations of coded_ block_pattern and dct_type. the immediate data is present only if indicated by thes e flags. the term ?reconstruction plane? in the following paragraphs refers to data that is written to the mc block?s local sram as a result of a given command. each reconstructed pel has a horizontal and vertical component that make up its position in the plane.
motion compensation specification 13 - 7 silicon motion ? , inc. SM731 confidential databook ih0 and ih1 indicate that the coded_block_pa ttern flag is set (idct data is present) for the one or two horizontal blocks that are processed. ih0 is used for the left most pels while ih1 is used for the right most. pel locations in the reconstruction plane are assigned to one of the coded block pattern (cbp) bits, namely ih0, ih1, or iv1. idct data is only used in the reconstruction calculation for a given location when its cbp bit is 1. otherwise, the idct data is either masked out or missing from the immediate data stream. iv0 and iv1 are the cbp bits used when two vertical blocks are present. in mpeg terms, iv0 can be thought of as indicating that block y2 is coded. iv1 can be thought of as indicating whether y3 is coded. idct data is re-ordered to be combined with prediction data (mrd bus). for this reason, th e cbp bits may not apply evenly to adjacent blocks as they do in the mpeg bitstream. their assignment to locations in th e reconstruction plane reflect th e change in the order of the idct data. tvb indicates that two vertical block as are processed at the same time. if tvb is high, ih0 and ih1 are used for the top half of the rows while iv0 and iv1 are used for the bottom half. in the top half, whether ih0 and ih1 is used will be dependent on the horizontal reconstruction pel position, thb and lhb. the same is true of iv0 and iv1 in the bottom half. tvb is not an indicator of the number of vertical rows for a command. the vsize [3:0] bits indicate this. although if tvb is high, vsize [3:0] bits indicate this. although if tvb is high, vsize [3:0] is used to determine the vertical half-way point for a command. lvb indicates that two blocks are vertically interleaved. th is is needed when frame prediction and field dct type data are used in a frame picture. when lvb is high, the even ro ws in the reconstruction plane are assigned to ih0 and ih1 while the odd rows are assigned to iv0 and iv1. for mpeg related applications, tvb and lvb will never both be set high. a command generator that sets them both will not cause a failure in the mc though. the result will be a union of the two modes. the top half of the rows will be interleaved while the bottom half will not. all of the bottom rows will be assigned to the iv0 and iv1 cbp bits. thb indicates that two horizontal blocks are processed at th e same time. when thb is high, either ih0 and iv0 will be assigned to the left most half of a reconstruction row, while ih 1 or iv1 will be used for the right most half. in the left half , whether ih0 and iv0 is used will be dependent on the row number, tvb and lvb. the same is true of ih1 and iv1 in the right half. thb is not an indicator of the number of horizontal pels in a row. the hsize [4:0] bits indicate this. although if thb is high, hsize [4:0] is used to determine the half-way point in a row. lhb indicates that two blocks are horizontally interleaved. th is is needed when chroma (cb and cr) is stored in a single plane to save memory bandwidth. when lhb is high, the upper 9 or 8 bits of the imm [17:0] bus are interpreted as a cb idct pel and ih0 and iv0 is used as a mask while the lower 9 or 8 bits are interpreted as cr with ih1 or iv1 as a mask. when a coded block pattern bit is 0 the corresponding immediate data is masked to 0 before being used in reconstruction calculations. unlike non-interleaved cases, data for the pels ma sked to 0 must be present in the immediate data stream even though their values are thrown out. when lhb is set high, the thb bit is ignored. setting both bits high has the same effect as setting lhb high and thb low.

3d drawing engine 14 - 1 silicon motion ? , inc. SM731 confidential databook chapter 14: 3d drawing engine SM731 incorporates a high end 3d drawing engine capable of rendering six million triangles and 250 million texels per second. the engine itself along with the several pipelines it incorporates have been comple tely redesigned from silicon motion?s previous 3d engine built inside lynx3dm (sm720). architectural delta from sm720  fast dma engine  20-cycle setup engine  dual texel pipelines  tile based rasterization  enable single cycle tri-linear mip-map and anisotropic filtering  add color destination cache  add 32-bit frame and z/stencil buffer  reduce page break penalty functionality delta from sm720  z clear value  single cycle multitexture  bump mapping w buffer  w based fog  stencil planes (up to 8 planes)
14 - 2 3d drawing engine silicon motion ? , inc. SM731 confidential databook figure 20: 3d engine dma setup rasterizer z engine tex t u r e pixel engine engine final pixel
3d drawing engine 14 - 3 silicon motion ? , inc. SM731 confidential databook dma and command interpreter SM731 incorporates a sophisticated dma and command interpreter engine through which all data to and from the 3d engine flows. the software driver builds buffer structures in agp memory containing all triangle data and commands for the 3d engine. from there on, SM731 hardware gathers these buffers, processes, and conveys status information back to the driver. feature set  fast dma engine  vertex buffer of 12 entries  supports flexible vertex format  supports vertex buffer  supports memory to memory blit  supports tiled memory to memory blit  accumulates and sends state changes to the entire 3d pipeline setup engine the setup engine completes a triangle parameter setup every 20 cycles. this gives 6 million triangles per second performance at 125 mhz. this performance is for a full featured tr iangle, i.e. a triangle with parameters: x, y, z, w, rs, gs, bs, as, rd, gd, bd, ad, s0, t0, s1, t1. feature set primitive types supported:  triangle list  triangle strip  triangle fan functionality features:  no cull, cull cw, cull ccw  up to two sets of color componen ts for diffused and specular colors  a set of registers for flat shading  up to two sets of texture coordinates  texture coordinate wrapping. wrapping is independent for each texture coordinate  screen space z  homogeneous space w rasterizer engine to improve memory interface performance, SM731 supports tile based rasterization. feature set  tiled rasterization  supports clipping window  supports w, z  supports specular and diffuse lighting  supports two textures texture engine two texture pipeline computes single pixel with two textur es each clock cycle. the pipeline gives 250 mtexels/second performance at 125 mhz. feature set  dual texture pipeline  floating point s, t, w computation  supports point sample, bi-linear, and tri-linear mip-map  supports bump mapping
14 - 4 3d drawing engine silicon motion ? , inc. SM731 confidential databook  supports texture compression supported texture formats:  argb8888  argb4444  argb1555  rgb565  dxt1, 2, 3, 4 and 5 pixel engine the pixel engine includes texture blending stages feature set  efficient pixel pipeline  supports both diffuse and specular color components  supports 16-bit and 32-bit frame buffer formats  supports multi-texture blend functions  supports color key function  supports both vertex and table based fog  supports alpha test function  supports all d3d source and destination blend modes  supports dithering for 16-bit frame buffer format z engine SM731 z engine supports stencil and fog. one z/stencil/fog pipeline computes z, stencil and fog values for one pixels per cycle. this gives us 125 mp/s. feature set  zero cycle z buffer clear  supports either screen space z or w  supported z formats: 16 and 24 bit fixed point format  supported w formats: 16-bit fixed point format and 24-bit floating point format  supports up to 8 stencil planes  supports table based fog with table size of 256 x 8  z and stencil cache
tv encoder 15 - 1 silicon motion ? , inc. SM731 confidential databook chapter 15: tv encoder the tv encoder is an ntsc/pal composite video/s-video enco der. it receives rgb inputs and converts to digital video signals based on ccir 624 format. the input video signal of the tv encoder is rgb 8-bit each. the sampling rate is corresponding to ccir 601, square pixel and 4fsc (ntsc only). the output video signals of the tv encoder are composite vi deo signal and s-video signals of 10-bit each. these output signals are over-sampled by a double frequency clock called clkx2. this feature helps to simplify external analog filtering. the tv encoder video timing is controlled by vertical sync and the horizontal sync input signals. the blank signal input is optional. if the blank signal input signal is pulled up, internal blanking control will be performed. macrovision 7.1.4 and closed captioning functions are included. key feature summary  ntsc/pal interlace mode digital video encoder  composite video and s-video digital output  ccir 601, square pixel and 4fsc (ntsc only) resolution rgb input  slave timing operation  interlace mode operation  2x over-sampling data output to simplify external analog filtering  selectable pedestal level oire/7.5ire for ntsc  macrovision function (version 7.1.4)  closed captioning function
15 - 2 tv encoder silicon motion ? , inc. SM731 confidential databook figure 21: tv encoder block diagram table 15: tv encoder block interface description excore-tv encoder for smi pin list pin name width i/o description r 8 i 4:4:4 sampled red data this data should be synchronized to the clkx1. g 8 i 4:4:4 sampled green data this data should be synchronized to the clkx1. b 8 i 4:4:4 sampled blue data this data should be synchronized to the clkx1. vsync_l 8 i vertical sync input, active low this goes low during the vertical sync intervals. hsync_l 1 i horizontal sync input, active low this goes low during the horizontal sync intervals. blank_l 1 i composite blanking input, active low. this goes low during the composite blanking intervals. if this signal is low, the rgb input data will be masked. clkx1 1 i pixel rate clock input this clock should be free-running, and will be synchronized to the clkx2. subcarrier generator 2x over- sampling + closed caption encoder + + + parallel interface timing controller color burst generator lpf lpf blank pedestal antitaping process control rgb to yuv converter yd[9:0] cvbs[9:0] cd[9:0] di[7:0] do[7:0] wid wdt mode[2:0] reset_l clkx1 blank_l hsync_l vsync_l r[7:0] g[7:0] b[7.0] clkx2 subcarrier generator 2x over- sampling + + closed caption encoder closed caption encoder + + + + + + parallel interface timing controller color burst generator color burst generator lpf lpf blank pedestal antitaping process control rgb to yuv converter yd[9:0] cvbs[9:0] cd[9:0] di[7:0] do[7:0] wid wdt mode[2:0] reset_l clkx1 blank_l hsync_l vsync_l r[7:0] g[7:0] b[7.0] clkx2
tv encoder 15 - 3 silicon motion ? , inc. SM731 confidential databook function descriptions video data input and sampling rate the video input data is rgb. each r, g, or b data is an 8-bit value. the range for the data is 0 to 255 respectively. the data is latched at positive edge of the clkx1. the tv encoder supports the following sampling rates: table 16: tv encoder sampling rates macrovision antitaping process the tv encoder supports the macrovision antitaping process function (u7.01). macrovision involves 3 functions which are the colorstripe process, pseudo sync /agc pulses with sync pulse amplitude reduction and eof back porch pulses. if the same line is assigned for closed captioning and the m acrovision process, all macrovision functions at the line are disabled for the closed captioning function. clkx2 1 i 2x pixel rate clock input this clock should be free-running. mode31mode select when mr[7] is set to 1, the mode is controlled by these input pins, otherwise the mode register (mr) setting will be taken. 000: ntsc ccir 100: pal ccir 001: ntsc square pixel 101: pal square pixel 010: ntsc 4fsc reset_l 1 i reset input, active low mv_en 1 i macrovision function enable di 8 i parallel i/f data input do 8 0 parallel i/f data output wid 1 i parallel i/f index strobe wdt 1 i parallel i/f data strobe cvbs 10 o s-video luminance data output yd 10 o composite video data output cd 10 o s-video chrominance data output video mode frequency total pixel/line total lines/frame ntsc ccir 601 13.5 mhz 858 525 square pixel 12.27 mhz 780 525 4fsc 14.32 mhz 910 525 pa l ccir 601 13.5 mhz 864 625 square pixel 14.75 mhz 944 625 pin name width i/o description
15 - 4 tv encoder silicon motion ? , inc. SM731 confidential databook the color stripe process function is applied to the composite video output and the chrominance signal output. this activated by mcr0[3] and controlled by mcr1 to mcr7 and mcr16 to mcr21. this function controls the color burst length and polarity. when this process is invoked during the burst blanking lines, no color burst signal is put. when the color burst length is assigned beyond the active video time, the color burst completes at the end of the blanking time. active video data then starts. the blanking time is controlled by the blank-l input pin and internal blanking. the pseudo sync/agc pulse function is applied to the composite video output and the s-video luminance output. the pseudo sync pulse is applied to the luminance signal. the agc pulses is a super-white positive going pulse. both of these pulses are output after color burst signal. the sync pu lse amplitude reduction changes the synchronizing level. this function is activated by mcr0[5] and mcr0[1:0], and controlled by mcr0[2], mcr8 to mcri4. the eof back porch pulse function generates a high level signal immediately after the trailing edge of the h-sync pulse. the value is 100ire for ntsc mode and 7oomv for pal mode. this function is activated by mcr0[4], and controlled by mcr[15]. closed captioning the closed captioning function is applied to the luminance da ta, and is shown at the composite video output and the s- video luminance output as follows. the level and timing corresponds to the eia standard eia-608. this function is controlled by the closed cap tioning registers. the closed captioned line is controlled as follows. table 17: closed captioning lines when the closed captioning function is enabled by the ccen register, the captioning data will be placed on the assigned line. when there is new data, the tv encoder outputs the new data. when there is no new data, a null code (80h) will be output. video mode odd field even field ntsc ccl + 4 ccl + 263 + 4 pal ccl + 1 ccl + 313 + 1
tv encoder 15 - 5 silicon motion ? , inc. SM731 confidential databook the odd field and even field are controlled separately. when one of 2 odd (even) data registers is written, the tv encoder recognizes new data for odd (even) field. the status bit ost(est) is set to 1. for normal usage, the new data is written when the status bit is 1. table 18: closed captioning odd field output data table 19: closed captioning even field output data video data output and over-sampling the tv encoder outputs composite video, luminance and ch rorninance signals. these outputs have 10-bit each, and are 2x over-sampled by the double frequency clock designated clkx2. this over-sampling simplifies external analog filtering. the output level and timing depend on the mode selected. synchronization this tv encoder operates in a slave mode. this means that the vertical sync and the horizontal sync are required for operation. the blanking signal is optional. the tv encoder will calculate the composite blanking time using the sync information. if the blank signal blank-l is pulled up, input data at the blanking time will be masked by the internal blanking signal. when the blanking signal is controlled, it's possible to shorten the active time for the input data. the tv encoder will mask the input data when the blank-l is low. the tv encoder automatically detects the odd/even field by sync information. sub-carrier generation the sub-carrier is internally generated using clkx1. depending on the sampling rate, the tv encoder will automatically calculate exact frequency. the sub-carrier phase is reset under the following conditions:  reset-l is low.  the first field changes to field 1 after reset- goes high.  the first field changes to field 1 after the tv encoder detects the mode change.  when genlock control is on. for this case, the sub-carrier pha se will be reset on every 4 fields for ntsc mode and 8 fields for pal mode. parallel bus i/f for internal register access, the parallel bus i/f is used. when the write index signal designated wid is high, the register address is latched. when the write data signal designated wdt is high, the data will be written to the latched address. enable status 1st output data 2nd output data cce[0] = 0 - no data no data cce[0] = 1 ost = 0 co_dt0 co_dt1 cce[0] = 1 ost = 1 80 (hex) 80 (hex) enable status 1st output data 2nd output data cce[0] = 0 - no data no data cce[0] = 1 est = 0 co_dt0 ce_dt1 cce[0] = 1 est = 1 80 (hex) 80 (hex)

power on configuration 16 - 1 silicon motion ? , inc. SM731 confidential databook chapter 16: power on configuration SM731 power-on configurations  bit md[63:0] and ma[11:0] have internal pull-up resistors on the i/o pads  0 = external pull-down resistor  1 = no external pull-down resistor table 20: power on configuration signal name read/write register address io address description md[37] config only pll selection. this is a hardware test feature which is used for debug purpose only) definition: pllvck = new,high performance pll pllvrck = existing pll from SM731 pllmck = existing pll from SM731 pllmck2 = new,high performance pll if md[37] config = 1 (default) vclk(video clock) = pllvck vrclk(lcd panel clock) = pllvrck mclk(engine clock) = pllmck mclk2(memory controller clock) = pllmck2 else vclk(video clock) = pllvrck vrclk(lcd panel clock) = pllvrck mclk(engine clock) = pllmck / 2 mclk2(memory controller clock) = pllmck * see also definition of ccr67[3:2] md[36:35] config only size of base memory selection 00=4mb 01=8mb 10=16mb 11=32mb md[34] config only being used when only one endian selected 0=small endian 1=big endian md[33] config only 0=only one endian 1=both endian md[32] reserved md[31] r/w mcr76[7] 3c5.76 0=reserved 1=normal (default) md[30:25] reserved md[24] r/w mcr76[0] 3c5.76 0=sdram interface 1=reserved
16 - 2 power on configuration silicon motion ? , inc. SM731 confidential databook note: for windows xp, windows nt, windows 9x, and windows me, the setting for md [36:35, 33] should be set at [111]. however, for windows ce, the setting for md [36:35, 33] should be set at [1,0,0]. md[23] 0=and with resetn to reset the free running clock divider for simulation and testing 1=normal (default) md[22} reserved mba[1] config only 0=enable c0000 eprom access 1=disable c0000 eprom access mba[0] config only 0=>pci config reg54[2]=1=>agp4x capable 1=>pci config reg54[2]=0=>not agp4x capable ma[11:8] r/w gpr70[3:0] 3c5.70 panel id 0000 = 640x480 tft 0001 = 800x600 tft 0010 = 1024x768 tft 0011 = 1280x1024 tft 0100 = 1600x1200 tft ma[7] r/w agp pad configuration 0=for 1.5v agp bus 1=for 3.3v agp bus ma[6] r/w lvds interface 0 = 18 bit tft 1 = 24 bit tft ma[5] r/w lvds panel 0 = msb of r,g,b at tx3-+. for 24 bits lvd s 1 = lsb of r,g,b at tx3-+. for 24 bits lvsds (hitachi type) ma[4] r/w panel sequence 0 = software panel on/off sequence 1 = hardware panel on/off sequence ma[3] r/w lvds configuration 0 = use double lvds configuration (two lvds chips on panel side) 1 = use single lvds configuration (only single lvds receiver on panel) ma[2:1] r/w 00=reserved 01=select non-lvds panel as primary panel display 10=select lvds1 as primary panel display 11=both lvds1 and non-lvds panel as primary panel display ma[0] r/w reserved for software purposes md[21:0] reserved signal name read/write register address io address description
register overview & usage 17 - 1 silicon motion ? , inc. SM731 confidential databook chapter 17: register overview & usage register types there are three general types of registers used on the SM731: pci configuration registers the pci configuration registers are listed in chapter 18: pci configuration space registers and accessed via the standard pci read/write protocols specified in the pci specification. memory mapped i/o registers all the i/o mapped registers within SM731 have been designed to be memory mapped as well. they are listed in chapter 19: standard vga registers and chapter 20: extended sm i io mapped registers. ?i/o? or ?memory? mapping is selected through pci configuration registers csr04 bit 0 and bit 1.  access via ?i/o? space is done by first writing the index value into the i/o register 3c4. thereafter, the indexed register can be accessed via i/o read/write to i/o address 3c5 example: register with index 0/h i/o write 0/h to 3c4 i/o read/write to/from 3c5  the procedure to access these registers via ?memory? mapped space is similar to ?i/o? space; with the index register being moved to memory address 6c03c4 and access register to 6c03c5. example: register with index 0/h memory write 0/h to 6c03c4 memory read/write to/from 6c03c5 memory mapped registers all the advanced functions of SM731 are controlled through memory mapped registers. such as the 2d and 3d motion compensation video registers, pci bus master control register s, tv encoder registers and 3d registers. the following diagram illustrates the memory mapped register address assignment. all the memory mapped registers can be accessed though the io port 3cd & 3cf. as described by the following table. 3ce = 20 address[7:0] 3ce = 21 address[15:8] 3ce = 22 address[23:16] 3ce = 23 address[31:24] * 3ce = 24 data[7:0]
17 - 2 register overview & usage silicon motion ? , inc. SM731 confidential databook * address [31:30] represent different ways of access [31:30] = 2'b00: linear memory map io access [31:30] = 2'b01: linear memory access mmio write use io write 3ce 20-27 to fill up the address and data. use io write 3ce 28 example: mmio address = 32'h00002800; data = 32'haabbccdd; byte enable = 4'b0000 mmio read use io write 3ce 20-23 to fill up the address. use io read with index 3ce=28 to activate and read 3ce 24-27 for data. example: mmio address = 32'h00002800 3ce = 25 data[15:8] 3ce = 26 data[23:16] 3ce = 27 data[31:24] 3ce = 28-2f activate write/read the ioaccess command 3cf[7:4] reserved 3cf[3:0] byte enable iowr_w(32'h3ce,32'h00000020); // mmio 20 word write iowr_w(32'h3ce,32'h00002821); // mmio 21 word write iowr_w(32'h3ce,32'h00000022); // mmio 22 word write iowr_w(32'h3ce,32'h00000023); // mmio 23 word write iowr_w(32'h3ce,32'h0000dd24); // mmio 24 word write iowr_w(32'h3ce,32'h0000cc25); // mmio 25 word write iowr_w(32'h3ce,32'h0000bb26); // mmio 26 word write iowr_w(32'h3ce,32'h0000aa27); // mmio 27 word write iowr_w(32'h3ce,32'h00000028); // mmio 28 with byte enable 4'b0000 iowr_w(32'h3ce,32'h00000020); // mmio 20 word write iowr_w(32'h3ce,32'h00002821); // mmio 21 word write iowr_w(32'h3ce,32'h00000022); // mmio 22 word write iowr_w(32'h3ce,32'h00000023); // mmio 23 word write iowr_b(32'h3ce,32'h00000028); // update 3ce index = 28 iord_b(32'h3cf,data); // execute io read. don't care the data iowr_b(32'h3ce,32'h00000024); // mmio 24 index write iord_b(32'h3cf,data); // mmio read data[7:0] iowr_b(32'h3ce,32'h00000025); // mmio 25 index write iord_b(32'h3cf,data); // mmio read data[15:8] iowr_b(32'h3ce,32'h00000026); // mmio 26 index write
register overview & usage 17 - 3 silicon motion ? , inc. SM731 confidential databook linear memory write use io write 3ce 20-27 to fill up the address and data. use io write 3ce 28 example: lmem address = 32'h40002800; data = 32'haabbccdd; byte enable = 4'b0000 linear memory read use io write 3ce 20-23 to fill up the address. use io read with index 3ce=28 to activate and read 3ce 24-27 for data. example: lmem address = 32'h40002800 iord_b(32'h3cf,data); // mmio read data[23:16] iowr_b(32'h3ce,32'h00000027); // mmio 27 index write iord_b(32'h3cf,data); // mmio read data[31:24] iowr_w(32'h3ce,32'h00000020); // mmio 20 word write iowr_w(32'h3ce,32'h00002821); // mmio 21 word write iowr_w(32'h3ce,32'h00000022); // mmio 22 word write iowr_w(32'h3ce,32'h00004023); // mmio 23 word write iowr_w(32'h3ce,32'h0000dd24); // mmio 24 word write iowr_w(32'h3ce,32'h0000cc25); // mmio 25 word write iowr_w(32'h3ce,32'h0000bb26); // mmio 26 word write iowr_w(32'h3ce,32'h0000aa27); // mmio 27 word write iowr_w(32'h3ce,32'h00000028); // mmio 28 with byte enable 4'b0000 iowr_w(32'h3ce,32'h00000020); // mmio 20 word write iowr_w(32'h3ce,32'h00002821); // mmio 21 word write iowr_w(32'h3ce,32'h00000022); // mmio 22 word write iowr_w(32'h3ce,32'h00004023); // mmio 23 word write iowr_b(32'h3ce,32'h00000028); // update 3ce index = 28 iord_b(32'h3cf,data); // execute io read. don't care the data iowr_b(32'h3ce,32'h00000024); // mmio 24 index write iord_b(32'h3cf,data); // mmio read data[7:0] iowr_b(32'h3ce,32'h00000025); // mmio 25 index write iord_b(32'h3cf,data); // mmio read data[15:8] iowr_b(32'h3ce,32'h00000026); // mmio 26 index write iord_b(32'h3cf,data); // mmio read data[23:16 iowr_b(32'h3ce,32'h00000027); // mmio 27 index write iord_b(32'h3cf,data); // mmio read data[31:24]
17 - 4 register overview & usage silicon motion ? , inc. SM731 confidential databook i/o mapped register mapped summary figure 22: i/o port 3c4 figure 23: i/o port 3?4 ibm vga sequencer registers index 0-4 system control registers index 10-1f power down control registers index 20-24 memory control registers index 60-63 clock or power down control registers in ppr block index 63 - 6f, index 94 - 9e usr0-3 ports control registers general purpose control registers index 70-73 scratch registers index 74-75 memory control registers index 76 monitor detect and crt/tv dac test registers index 7a-7d crt hwc pop icon registers index 80-8d crt pop icon registers index 90-93 ibm vga crtc registers index 0-26 extended crtc control registers index 30-3c scratch registers index 3d-3f crt shadow registers index 40-4d tv encoder control registers index 6x-8x screen centering & expansion control index 90-9f; index a0-ad
register overview & usage 17 - 5 silicon motion ? , inc. SM731 confidential databook figure 24: memory mapped address diagram mmio_base 2d3d reg ports 0000_0000-0000_07ff 2k video reg port 0000_0800-0000_0fff 2k vidcap reg port 0000_1000-0000_17ff 2k mc icmd reg port 0000_1800-0000_1fff 2k md idct reg port 0000_2000-0000_27ff 2k mas mif reg port 0000_2800-0000_2fff 2k 2d3d master reg port 0000_3000-0000_37ff 2k mc core reg port 0000_3800-0000_3fff 2k mc icmd data port 0000_4000-0000_47ff 2k mc idct data port 0000_4800-0000_4fff 2k mas mif data port 0000_5000-0000_57ff 2k panel control registers 0000_5800-0000_5fff 2k de data port 0000_6000_0000_7fff 8k 2d3d dma data port 0001_0000-0008_ffff 512k memory map io space 000c_0000-000f_ffff 256k additional de data port 01_00000-00_01_fffff 1mb mmio_base (cfg14)
17 - 6 register overview & usage silicon motion ? , inc. SM731 confidential databook figure 25: frame buffer memory space (32mb for single endian, 64mb for bi-endian) 0 up to 64 mb configurationable memory size 4, 8, 16, 32, or 64mb fb_base (cfg10) frame buffer (up to 64 mb)
pci configuration space registers 18 - 1 silicon motion ? , inc. SM731 confidential databook chapter 18: pci configuration space registers table 21: pci configuration registers quick reference summary of registers page csr00: vendor id and device id 18 - 2 csr04: command and status 18 - 2 csr06: status 18 - 3 csr08: revision id and class code 18 - 4 csr0c: latency timer 18 - 4 csr10: linear frame buffer base address register 18 - 5 csr2c: subsystem id and subsystem vendor id 18 - 6 csr30: expansion rom base address 18 - 7 csr34: power down capability pointer 18 - 7 csr3c: interrupt pin and interrupt line 18 - 8 csr40: power down capability register 18 - 8 csr44: power down capability data 18 - 8 csr50: agp capability pointer 18 - 9 csr54: agp status pointer 18 - 9 csr58: agp command register 18 - 10 lock: extended register write protect control 18 - 11
18 - 2 pci configuration space registers silicon motion ? , inc. SM731 confidential databook pci configuration space registers the pci specification defines the configuration space for auto-configuration (plug-and-play), device and memory relocation. csr00: vendor id and device id read only address: 00h power-on default: 0730126fh this register specifies the vendor id bit 31:16 device id these bits are hardwired to 0730h to identify the device as SM731. bit 15:0 vendor id these bits are hardwired to 126fh to identify as silicon motion ? , inc. csr04: command and status read/write address: 04h note: reserved bits are read only power-on default: 02300000h this register controls which types of pci command cycles are supported by SM731. bit 31 (dpe) data parity error detected (read only) 0 = correct 1 = error detected bit 30:29 reserved bit 28 (dta) received target abort (read only) 0 = correct 1 = abort detected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 device id 1514131211109876543210 vendor id 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 dpe r dta r devsel reserved 66c ncd reserved 1514131211109876543210 reserved pse mwr r pbm ms io
pci configuration space registers 18 - 3 silicon motion ? , inc. SM731 confidential databook bit 27 reserved bit 26:25 (devsel) timing select medium (read only) bit 24:22 reserved bit 21 66 mhz capable (read only) bit 20 (ncd) new capability definition (read only) bit 19:6 reserved bit 5 (pse) palette snooping enable (read/write) 0 = disable 1 = enable bit 4 (mwr) memory write and invalidate enable (read/write) 0 = disable 1 = enable bit 3 reserved bit 2 (pbm) pci bus master enable (read/write) 0 = disable 1 = enable bit 1 (ms) memory space access enable (read/write) 0 = disable 1= enable bit 0 (io) io space access enable (read/write) 0 = disable 1 = enable csr06: status read only address: 06h power-on default: 20h this register controls device select timing status, detect parity status, and detects target abort status for SM731. in order t o clear any bit of this register, you must write a "1" to that particular bit. bit 31:16 reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 dpe reserved dta r ts reserved
18 - 4 pci configuration space registers silicon motion ? , inc. SM731 confidential databook bit 15 detect parity error (dpe) bit 14:13 reserved (r) bit 12 detect target abort for master mode (dta) bit 11 reserved (r) bit 10:9 ~devsel timing select (ts) 01 = medium speed (hardwired) bit 8:0 reserved csr08: revision id and class code read only address: 08h power-on default: 030000a0h this register specifies the silicon revision id and the class code that the silicon supports. bit 31:24 base class code 03h = for video controller bit 23:16 subclass code 00h = vga bit 15:8 register level programming interface 00h = hardwired setting bit 7:0 revision id for example, a0h = revision a; b0h = revision b csr0c: latency timer read only address: 0dh power-on default: 00h this register specifies the latency timer that SM731 supports for burst master mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 base class code subclass code 1514131211109876543210 reg level programming interface revision id
pci configuration space registers 18 - 5 silicon motion ? , inc. SM731 confidential databook bit 31:16 reserved bits 15:8 (lt) latency timer (read/write) default = 00h bit 7:0 reserved csr10: linear frame buffer base address register read/write address: 10h (note: reserved bits are read only) power-on default: 0000000h this register specifies the pci configuration space for address relocation bit 31:26 linear addressing memory base address. memo ry segment allocated within 64 mb boundary if 4 mb with one endian: bit 25:22 = fba (read/write) if 8 mb with one endian: bit 25:23 = fba (read/write) bit 22 = 0b (read only) if 16 mb with one endian: bit 25:24 = fba (read/write) bit 23:22 = 00b (read only) if 32 mb with one endian: bit 25 = fba (read/write) bit 24:22 = 000b (read only) if 4 mb with big and small endian: bit 25:23 = fba (read/write) bit 22 = 0b (read only) if 8 mb with big and small endian: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 latency timer reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 linear addressing memory base reserved 1514131211109876543210 reserved msi
18 - 6 pci configuration space registers silicon motion ? , inc. SM731 confidential databook bit 25:24 = fba (read/write) bit 23:22 = 00b (read only) if 16 mb with big and small endian: bit 25 = fba (read/write) bit 24:22 = 000b (read only) if 32 mb with big and small endian: bit [25:22] = 0000b (read only) bit 21:1 linear frame buffer base address (read only) default = 000000h bit 0 (mb) memory base read (only) default = 0b csr14: base address register for memory map address read/write address: 14h (note: reserved bits are read only) power-on default: 0000000h this register specifies the pci configuration space for address relocation bit 31:21 (fba) memory map address base address (r/w/r) if one endian: bit [31:21] = fba (read/write) if big and small endian: bit [31:22] = fba (read/write) bit [21] = 0b (read only) bit 20:1 (aba) memory map address base address (read only) default = 000000h bit 0 (mb) memory base (read only) default = 0b csr2c: subsystem id and subsystem vendor id read only address: 2ch power-on default: 00000000h this register specifies both the subsystem device id and the subsystem vendor id. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 linear addressing memory base 1514131211109876543210 reserved mb
pci configuration space registers 18 - 7 silicon motion ? , inc. SM731 confidential databook bit 31:16 subsystem id. this system id is written by the system bios during post bit 15:0 subsystem vendor id csr30: expansion rom base address read/write address: 30h power-on default: 00000000h this register specifies the expansion rom base address. (note: reserved bits are read only.) bit 31:16 rom base address. memory segment allocated for bios rom in 64kb boundary [15:0] bit 15:1 reserved bit 0 bios address decode enable. this bit is valid on ly if memory space access is enabled (csr04 bit 1 = 1) 0 = disable 1 = enable csr34: power down capability pointer read only address: 34h power-on default: 00000040h this register contains the address where pci power down management registers are located bit 31:0 capability pointer contains the address where the pci power down management register is located. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 subsystem id 1514131211109876543210 subsystem vendor id 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rom base address 1514131211109876543210 reserved bios 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 power down capability pointer 1514131211109876543210 power down capability pointer
18 - 8 pci configuration space registers silicon motion ? , inc. SM731 confidential databook csr3c: interrupt pin and interrupt line read/write address: 3ch power-on default: 00000000h this register specifies the pci interrupt pin and line. bit 31:16 reserved bit 15:8 interrupt pin (read only) bit 7:0 interrupt line (read/write) csr40: power down capability register read only address: 40h power-on default: 0601x001h this register contains the address where pci power down management capabilities. bit 31:16 pci power down management capability = 0601h offset 2 bit 15:8 if agp enabled: next capability pointer link list = 50h offset 1 if pci only: no more extra capability pointer = 00h bit 7:0 pci power down management capability id= 01h offset 0 csr44: power down capability data read/write address: 44h power-on default: 00h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 interrupt pin (read only) interrupt line (read/write) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 pci power down management capability (0601h) 1514131211109876543210 next capability pointer link list pci power down mgmt capability (01h)
pci configuration space registers 18 - 9 silicon motion ? , inc. SM731 confidential databook this register contains the address where pci power down management control, status and data are located. bit 31:24 data read only. offset 7 bit 23:16 reserved =00 offset 6 bit 15:2 pci power down management control/status offset 4 bit 1:0 power down management control and status 00 = power down management state d0 01 = power down management state d1 10 = power down management state d2 11 = power down management state d3 csr50: agp capability pointer read/write address: 50h power-on default: 00200002h bit 31:24 reserved bit 23:16 major/minor revision = 20h bit 15:8 next capability pointer = 00h bit 7:0 agp capability id = 02h csr54: agp status pointer read only address: 54h power-on default: 00000000h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 data reserved 1514131211109876543210 pci power down mgmt control/status pds 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved major/minor revision 1514131211109876543210 next capability pointer agp capability id
18 - 10 pci configuration space registers silicon motion ? , inc. SM731 confidential databook bit 31:24 request depth (= 0f) bit 23:10 reserved bit 9 side bus addressing enabled (sba) (= 1) bit 8:6 reserved bit 5 4 gb support (= 0) bit 4 fast write enabled (= 0) bit 3 reserved (r) bit 2 agp4x capable (read only) 1 if power-on configured mba[0] = 0 0 if power-on configured mba[0] = 1 bit 1 agp2x capable (read only) 1 if scr26[5] = 0 0 if scr26[5] = 1 bit 0 agp1x capable (read only) 1 if scr26[4] = 0 0 if scr24[4] = 1 csr58: agp command register read/write address: 58h power-on default: 00000000h bit 31:28 reserved (maximum of 16 requests) bit 27:24 request depth 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 request depth reserved 1514131211109876543210 reserved sba reserved 4gs fwe r agp4xagp2xagp1x 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved request depth reserved 1514131211109876543210 reserved sba agp reserved 4gs fwe r data rate
pci configuration space registers 18 - 11 silicon motion ? , inc. SM731 confidential databook bit 23:10 reserved bit 9 side bus addressing enabled (sba) 0 = disable 1 = enable bit 8 agp enabled 0 = disable 1 = enable bit 7:6 reserved bit 5 4 gb support bit 4 fast write enabled bit 3 reserved (r) bit 2:0 data rate 001 = 1x 010 = 2x 100 = 4x extended smi registers lock: extended register write protect control read/write address: 3c3h power-on default: 00h this register specifies write protect controls for the smi exte nded registers. smi extended registers are write-protected. in order to write to the smi extended registers, one must write bit [7:5] = 010b. bit 7:5 write protect enable (wpe) 101 = all smi extended registers are write-protected 010 = enable writes to smi extended registers others = maintain previous state bit 4:0 reserved 76543210 wpe reserved

standard vga registers 19 - 1 silicon motion ? , inc. SM731 confidential databook chapter 19: standard vga registers table 22: standard vga registers quick reference summary of registers page general registers misc: miscellaneous output register 19 - 4 isr0: input status register 0 19 - 4 isr1: input status register 1 19 - 5 fcr: feature control register 19 - 5 sequencer register seqx: sequencer index register 19 - 6 seq00: reset register 19 - 6 seq01: clocking mode register 19 - 7 seq02: enable write plane register 19 - 7 seq03: character map select register 19 - 8 seq04: memory mode register 19 - 8 crtc controller registers crtx: crtc controller index register 19 - 9 crt00: horizontal total register 19 - 9 crt01: horizontal display end register 19 - 10 crt02: horizontal blank start register 19 - 10 crt03: horizontal blank end register 19 - 10 crt04: horizontal sync pulse start register 19 - 11 crt05: end horizontal sync pulse register 19 - 11 crt06: vertical total register 19 - 12 crt07: overflow vertical register 19 - 12 crt08: preset row scan register 19 - 13 crt09: maximum scan line register 19 - 13 crt0a: cursor start scan line register 19 - 14 crt0b: cursor end scan line register 19 - 14 crt0c: display start address high register 19 - 15 crt0d: display start address low register 19 - 15
19 - 2 standard vga registers silicon motion ? , inc. SM731 confidential databook crt0e: cursor location high register 19 - 15 crt0f: cursor location low register 19 - 16 crt10: vertical sync pulse start register 19 - 16 crt11: vertical sync pulse end register 19 - 16 crt12: vertical display end register 19 - 17 crt13: offset register 19 - 17 crt14: underline location register 19 - 18 crt15: vertical blank start register 19 - 18 crt16: vertical blank end register 19 - 19 crt17: crt mode control register 19 - 19 crt18: line compare register 19 - 20 crt22: graphics controller data latches readback register 19 - 20 crt24: attribute controller toggle readback register 19 - 20 crt26: attribute controller index readback register 19 - 21 graphics controller registers grxx: graphics controller index register 19 - 21 grx00: set/reset register 19 - 22 grx01: enable set/reset register 19 - 22 grx02: color compare register 19 - 23 grx03: data rotate/rop register 19 - 23 grx04: read plane select register 19 - 23 grx05: graphics mode register 19 - 24 grx06: graphics miscellaneous register 19 - 25 grx07: color don't care plane register 19 - 25 grx08: bit mask register 19 - 26 attribute controller registers atrx: attribute controller index register 19 - 26 atr00-0f: palette register 19 - 27 atr10: attribute mode control register 19 - 27 atr11: overscan color register 19 - 28 atr12: color plane enable register 19 - 28 atr13: horizontal pixel panning register 19 - 29 atr14: color select register 19 - 30 ramdac registers 3c6: dac mask register 19 - 30 3c7w: dac address read register 19 - 31 3c7r: dac status register 19 - 31 summary of registers page
standard vga registers 19 - 3 silicon motion ? , inc. SM731 confidential databook 3c8: dac address write register 19 - 31 3c9: dac data register 19 - 32 summary of registers page
19 - 4 standard vga registers silicon motion ? , inc. SM731 confidential databook standard vga registers in the following registers description, a '?' in an address stands for a hexadecimal value of either 'b' or 'd'. if bit 0 of th e miscellaneous output register is set to 1, the address is ba sed at 3dxh for color emulation. if bit 0 of the miscellaneous output register is set to 0, the address is based at 3bxh for monochrome emulation. general registers misc: miscellaneous output register write only address: 3c2h read only address: 3cch power-on default: 00h bit 7 vertical sync polarity select (vsp) 0 = positive vertical sync polarity 1 = negative vertical sync polarity bit 6 horizontal sync polarity select (hsp) 0 = positive horizontal sync polarity 1 = negative horizontal sync polarity bit 5 odd/even memory page select (oem) 0 = select lower 64k page of memory 1 = select upper 64k page of memory bit 4 reserved (r) bit 3:2 video clock select 00 = select 25.175mhz for 640 dots/line mode 01 = select 28.322mhz for 720 dots/line mode 10 = reserved (enable external clock source) 11 = reserved (enable external clock source) bit 1 enable video ram access from cpu (evr) 0 = disable video ram access from cpu 1 = enable video ram access from cpu bit 0 i/o address select (io) 0 = select monochrome mode. address based at3bxh. 1 = select for color mode. address based at 3dxh isr0: input status register 0 read only address: 3c2h power-on default: undefined 76543210 vsp hsp oem r video clock evr io
standard vga registers 19 - 5 silicon motion ? , inc. SM731 confidential databook bit 7 crt vertical retrace interrupt (crt) 0 = vertical retrace interrupt is cleared 1 = vertical retrace interrupt is pending. bit 6:5 reserved bit 4 monitor detect status (mds) 0 = monochrome display is detected 1 = color display is detected bit 3:0 reserved isr1: input status register 1 read only address: 3?ah power-on default: undefined bit 7:6 reserved bit 5:4 color plane diagnostics these bits return two of the 8 video outputs vid0-v id7, as selected by color plane enable register [5:4] bit 3 vertical retrace status (vrs) 0 = in display mode 1 = in vertical retrace mode bit 2:1 reserved (r) bit 0 display enable 0 = in display mode 1 = not in display mode. (it is either in horizontal or vertical retrace mode) fcr: feature control register write only address: 3?ah read only address: 3cah power-on default: 00h 76543210 crt reserved mds reserved 76543210 reserved color plane vrs r display enable
19 - 6 standard vga registers silicon motion ? , inc. SM731 confidential databook bit 7:4 reserved bit 3 vertical sync control 0 = vsync output is enabled 1 = vsync output is logical 'or' of vsync and vertical display enable bit 2:0 reserved sequencer register seqx: sequencer index register read/ write address: 3c4h power-on default: undefined bit 7:4 reserved bit 3:0 sequencer address/index the sequencer address register is written with the index value of the sequencer register to be accessed. seq00: reset register read/ write address: 3c5h, index: 00h power-on default: 00h bit 7:2 reserved bit 1 synchronous reset (sr) 0 = sequencer is cleared and halted synchronously 1 = normal operating mode bit 0 asynchronous reset (ar) 0 = sequencer is cleared and halted asynchronously 1 = normal operating mode 76543210 reserved vsc reserved 76543210 reserved sequencer address/index 76543210 reserved sr ar
standard vga registers 19 - 7 silicon motion ? , inc. SM731 confidential databook seq01: clocking mode register read/ write address: 3c5h, index: 01h power-on default: 00h bit 7:6 reserved bit 5 screen off (so) 0 = normal operating mode 1 = screen is turned off but sync signals remain active bit 4 video serial shift select (vs) 0 = load video serializer every or every other character or clock, depending on bit2 of this register. 1 = load video serializer every 4th character clock bit 3 dot clock select (dcs) 0 = normal dot clock select by vclk input frequency 1 = dot clock is divided by 2 (320/360 pixel mode) bit 2 shift load (sl) 0 = load video serializer every character or clock 1 = load video serializer ev ery other character or clock bit 1 reserved (r) bit 0 8/9 dot clock (dc) 0 = 9 dot wide character clock 1 = 8 dot wide character clock seq02: enable write plane register read/ write address: 3c5h, index: 02h power-on default: 00h bit 7:4 reserved bit 3:0 enable writing to memory maps 3 through 0 (respectively) 0 = disable writing to corresponding plane 1 = enable writing to corresponding plane 76543210 reserved so vs dcs sl r dc 76543210 reserved enable writing
19 - 8 standard vga registers silicon motion ? , inc. SM731 confidential databook seq03: character map select register read/ write address: 3c5h, index: 03h power-on default: 00h bit 7:6 reserved bit 5,3,2 select character map a (scma) this value select the portion of plane 2 used to generate text character when bit 3 of this register = 0, according to the following table: bit 4,1,0 select character map b (scmb) this value select the portion of plane 2 used to generate text character when bit 3 of this register = 1, according to the same table as character map a seq04: memory mode register read/ write address: 3c5h, index: 04h power-on default: 00h bit 7:4 reserved bit 3 chained 4 map (cm) 0 = enable odd/even mode 1 = enable chain 4 mode. uses the two lower bits of cpu address to select plane in video memory as follows: 76543210 reserved scm scmb scma scma scmb scmb bit 5,3,2 font table location 000 first 8k of plane 2 100 second 8k of plane 2 001 third 8k of plane 2 101 fourth 8k of plane 2 010 fifth 8k of plane 2 110 sixth 8k of plane 2 011 seventh 8k of plane 2 111 eighth 8k of plane 2 76543210 reserved cm ssa evm r
standard vga registers 19 - 9 silicon motion ? , inc. SM731 confidential databook bit 2 select sequential addressing mode (ssa). this bit affects only cpu write data accesses into video memory. bit 3 of this register must be 0 for this bit to be effective. 0 = enable the odd/even addressing mode. even addresses access planes 0 and 2, and odd addresses access plane 1 and 3 1 = enable system to use a sequential addressing mode bit 1 extended video memory enable (evm) 0 = memory access restricted to 16/32k 1 = enable extended video memory access. allows complete memory access to 256k bit 0 reserved (r) crtc controller registers the crtc registers are located at two locations in i/o addr ess space. these registers are accessed by first writing to the index register (3?4h), then writing to the data register (3?5h). the i/o address is either 3bxh or 3dxh depending on bit 0 of the miscellaneous output register at 3c2h. crtx: crtc controller index register read/write address: 3?4h power-on default: 00h this register is loaded with a binary value that indexe s the crtc controller register where data is to be accessed. bit 7:5 reserved bit 4:0 crtc address index these bits specify the crtc register to be addressed. its value is programmed in hexadecimal. crt00: horizontal total register read/write address: 3?5h, index 00h power-on default: undefined ma1 ma0 plane selected 00 0 01 1 10 2 11 3 76543210 reserved crtc address index
19 - 10 standard vga registers silicon motion ? , inc. SM731 confidential databook this register defines the number of character clocks from hsync going active to the next hsync going active. bit 7:0 horizontal total this value = (number of character clocks per scan line) - 5. crt01: horizontal display end register read/write address: 3?5h, index 01h power-on default: undefined this register defines the number of character clocks for one horizontal line active display. this register is locked when fpr33 (sc5h, index 33) bit 5 = 1. please refer to fpr33 register. bit 7:0 horizontal display enable this value = (number of character clocks during active display) - 1. crt02: horizontal blank start register read/write address: 3?5h, index 02h power-on default: undefined this register defines the number of character cl ocks at which horizontal ~blank is asserted. bit 7:0 horizontal blank start this value = character value at which ~blank signal becomes active. crt03: horizontal blank end register read/write address: 3?5h, index 03h power-on default: undefined this register defines the display enable skew and pulse width of ~blank signal. 76543210 horizontal total 76543210 horizontal display enable 76543210 horizontal blank start 76543210 r display enable horizontal blank end
standard vga registers 19 - 11 silicon motion ? , inc. SM731 confidential databook bit 7 reserved bit 6:5 display enable skew. these 2 bits define the display enable signal skew timing in relation to horizontal synchronization pulses. bit 4:0 horizontal blank end horizontal blank end has a 6-bit value. this register contains the least significant 5-bits of this value. bit 6 of this value is at crtc index 05 bit 7. crt04: horizontal sync pulse start register read/write address: 3?5h, index 04h power-on default: undefined this register is used to adjust screen position horizontally and to specify the position at which hsync is active. bit 7:0 horizontal sync pulse start this value = character clock count value at which hsync becomes active. crt05: end horizontal sync pulse register read/write address: 3?5h, index 05h power-on default: undefined this register defines the horizontal sync skew and pulse width of hsync signal. bit 7 horizontal blank end bit 5. this bit is end horizontal blank bit 5. (hbe) bit 6:5 horizontal sync skew. (hss) these 2-bits define the hsync signal skew timing in relation to horizontal synchronization pulses. deskw1 deskw0 character clock skew 00 0 01 1 10 2 11 3 76543210 horizontal sync pulse start 76543210 hbe hss horizontal sync end
19 - 12 standard vga registers silicon motion ? , inc. SM731 confidential databook bit 4:0 horizontal sync end horizontal sync end has a 5-bit value. this value defines the character clock counter value at which hsync signal becomes inactive. crt06: vertical total register read/write address: 3?5h, index 06h power-on default: undefined this register defines the number of scan lines from vsync going active to the next vsync going active. vertical total has a 11-bit value. bit 8 of this value is located at crt07 bit 0. bit 9 of this value is located at crt07 bit 5. bit 10 of thi s value is located at crt30 bit 3. bit 7:0 vertical total vertical total has a 11-bit value. this register contains the least significant 8-bits of this value. this value = (number of scan lines from vsync going active to the next vsync) - 2. bit 8 is in crt07 bit 0. bit 9 is in crt 07 bit 5. bit 10 is in crt30 bit 3. crt07: overflow vertical register read/ write address: 3?5h, index: 07h power-on default: undefined this register specifies the crtc vertical overflow registers. bit 7 vertical sync start bit 9 (vss) bit 6 vertical display enable end bit 9. this bit is locked when fpr33 (sc5h, index 33) bit 5 = 1. please refer to fpr33 register. (vde) bit 5 vertical total bit 9 (vt) bit 4 line compare bit 8 (lc) hsskw1 hsskw0 character clock skew 00 0 01 1 10 2 11 3 76543210 vertical total 76543210 vss vde vt lc vbs vss vde vt
standard vga registers 19 - 13 silicon motion ? , inc. SM731 confidential databook bit 3 vertical blank start bit 8 (vbs) bit 2 vertical sync start bit 8 (vss) bit 1 vertical display enable end bit 8. this bit is locked when fpr33 (sc5h, index 33) bit 5 = 1. (vde) bit 0 vertical total bit 8 (vt) crt08: preset row scan register read/write address: 3?5h, index 08h power-on default: undefined this register is used for panning and text scrolling. bit 7 reserved (r) bit 6:5 byte panning control. these 2-bits controls the number of bytes to pan. bit 4:0 preset row scan count these bits preset the vertical row scan counte r once after each vertical retrace. this counter is automatically incremented by 1 after each horizontal sync period. once the maximum row scan count is reached, this counter is cleared. this is useful for smoothing vertical text scrolling. crt09: maximum scan line register read/write address: 3?5h, index 09h power-on default: undefined this register defines the maximum number of scan lines per character row and provides one scanning control and two overflow bits bit 7 enable double scan (eds) 76543210 r byte planning preset row scan count bpc1 bpc0 operation 00 normal 0 1 1 byte left shift 1 0 2 bytes left shift 1 1 3 bytes left shift 76543210 eds lc vb maximum scan line
19 - 14 standard vga registers silicon motion ? , inc. SM731 confidential databook 0 = normal operating 1 = enable double scan. the row scan counter is clocked at half of the horizontal scan rate. bit 6 line compare register bit 9 (lc) bit 5 vertical blank start register bit 9 (vb) bit 4:0 maximum scan line this value equals to the total number of scan lines per character row - 1 crt0a: cursor start scan line register read/write address: 3?5h, index 0ah power-on default: undefined this register defines the row scan of a character line at which the cursor begins and enable/disable cursor. bit 7:6 reserved bit 5 enable cursor (ec) 0 = cursor is on 1 = cursor is off bit 4:0 cursor start scan line this value equals to the starting cursor row within the character box. if this value is programmed with a value greater than the cursor end scan line register (3?5h, index 0bh), no cursor will be displayed. crt0b: cursor end scan line register read/write address: 3?5h, index 0bh power-on default: undefined this register defines the row scan of a character line at which the cursor begins and enable/disable cursor. bit 7 reserved (r) bit 6:5 cursor skew. these 2 bits defines the cursor delay skew, which moves the cursor to the right, in character clock. 76543210 reserved ec cursor start scan line 76543210 r cursor skew cursor end scan line
standard vga registers 19 - 15 silicon motion ? , inc. SM731 confidential databook bit 4:0 cursor end scan line this value equals to the ending cursor row within th e character box. if this va lue is programmed with a value less than the cursor start scan line register (3?5h, index 0ah), no cursor will be displayed. crt0c: display start address high register read/write address: 3?5h, index 0ch power-on default: undefined this register defines the high order first address after a vert ical retrace at which the display on the screen begins on each screen refresh. this value is a 19-bit value. bit [18:16] are located in crt30 bit [6:4]. bi t [7:0] are located in crt0d. bit 7:0 display start address [15:8] this register is the high order byte of the address [15:8]. crt0d: display start address low register read/write address: 3?5h, index 0dh power-on default: undefined this register defines the low order first address after a ver tical retrace at which the display on the screen begins on each screen refresh. this value is a 19-bit value. bit [18:16] are in crt30 bit [6:4]. bit [15:8] are in crt0c. bit 7:0 start address [7:0] this register is the low order byte of the address [7:0]. crt0e: cursor location high register read/write address: 3?5h, index 0eh power-on default: undefined cskw1 cskw0 character clock skew 00 0 01 1 10 2 11 3 76543210 diplay start address [15:8] 76543210 start address [7:0]
19 - 16 standard vga registers silicon motion ? , inc. SM731 confidential databook this register defines the high order cursor location address. this value is a 19-bit value along with crt30 bit[6:4] are the high order bits of the address. bit 7:0 cursor location high this register is the high order byte of the cursor location address. crt0f: cursor location low register read/write address: 3?5h, index 0fh power-on default: undefined this register defines the low order cursor location address. bit 7:0 cursor location low this register is the low order byte of the cursor location address. crt10: vertical sync pulse start register read/write address: 3?5h, index 10h power-on default: undefined this register is used to adjust screen position vertically and to specify the position at which vsync is active. bit 10 of this value is in crt30 bit 0. bit 9 of this value is in crt07 bit 7. bit 8 of this value is in crt07 bit 2. bit 7:0 vertical sync pulse start vertical sync start has a 11-bit value. this register contains the least significant 8 bits of this value. this value = number of scan lines at which vsync becomes active. crt11: vertical sync pulse end register read/write address: 3?5h, index 11h power-on default: 0xh. this register is used to control vertical interrupt, vertical sync end crt0-7 write protect. 76543210 cursor location high 76543210 cursor location low 76543210 vertical sync pulse start
standard vga registers 19 - 17 silicon motion ? , inc. SM731 confidential databook bit 7 lock writing to crtc registers: crt00-07. (lw) 0 = enable writing to crtc registers are 1 = disable writing to crtc registers, except crt07 bit 4 (line compare) bit 6 refresh cycle select (3/5) (rcs) 0 = 3 dram refresh cycles per horizontal scan line 1 = 5 dram refresh cycles per horizontal scan line bit 5 disable vertical interrupt (dvi) 0 = vertical retrace interrupt enabled 1 = vertical retrace interrupt disabled bit 4 clear vertical interrupt (cvi) 0 = vertical retrace interrupt is cleared 1 = vertical retrace interrupt. this allows an inte rrupt to be generated at the end of active vertical display. bit 3:0 vertical sync pulse end this value = number of scan lines at which vsync becomes inactive. crt12: vertical display end register read/write address: 3?5h, index 12h power-on default: undefined this register defines the number of scan line where the display on the screen ends. bit 10 of this value is in crt30 bit 2. bit 9 of this value is in crt07 bit 6. bit 8 of this value is in crt07 bit 1. this register is locked when fpr33 (sc5h, index 33) bit 5 = 1. please refer to fpr33 register. bit 7:0 vertical display end vertical display end has a 11-bit value. this register contains the least significant 8-bits of this value. this value = (number of scan lines during active display) - 1. crt13: offset register read/write address: 3?5h, index 13h power-on default: undefined 76543210 lw rcs dvi cvi vertical sync pulse end 76543210 vertical display end
19 - 18 standard vga registers silicon motion ? , inc. SM731 confidential databook this register defines the logical line width of the screen. th e starting memory address for the next display row is larger than the current row by two (in byte mode), four (in word mode), or eight (in double word mode) times this offset. bit 7:0 logical screen width logical screen width has a 10-bit value. this register contains the least significant 8-bits of this value. the addressing mode is specified by bit 6 of crt14 and bit 3 of crt17. crt14: underline location register read/write address: 3?5h, index 14h power-on default: undefined this register defines the horizontal row scan position of underline and display buffer addressing modes. bit 7 reserved (r) bit 6 double word mode select (dws) 0 = the memory address are byte or word addresses 1 = the memory address are double word addresses bit 5 count by 4 select (cs) 0 = the memory address counter depends on bit 3 of crt17 1 = the memory address counter is incremented every four character clocks bit 4:0 under line location under line location has a 5-bit value. this value = (scan line count of a character row on which an underline occurs) - 1. crt15: vertical blank start register read/write address: 3?5h, index 15h power-on default: undefined this register defines the number of scan lines at which vertical blank is asserted. bit 10 of this value is in crt30 bit 1. bit 9 of this value is in crt09 bit 5. bit 8 of this value is in crt07 bit 3. 76543210 logical screen width 76543210 r dws cs under line location 76543210 vertical blank start
standard vga registers 19 - 19 silicon motion ? , inc. SM731 confidential databook bit 7:0 vertical blank start vertical blank start has a 11-bit value. this register contains the least significant 8-bits of this value. this value = (scan line count at which vertical blank signal becomes active) - 1. crt16: vertical blank end register read/write address: 3?5h, index 16h power-on default: undefined this register defines the number of scan lines at which vertical blank is de-asserted. bit 7:0 vertical blank end vertical blank end is a 8-bit value. this value = [(scan line count at which vertical blank signal becomes active) -1)] + (desired width of vertical blanking pulse in scan lines) crt17: crt mode control register read/write address: 3?5h, index 17h power-on default: undefined this register defines the controls for crt mode. bit 7 ~rst hardware reset for horizontal and vertical sync (hr) 0 = horizontal and vertical sync outputs inactive 1 = horizontal and verti cal sync outputs active bit 6 byte address mode select (bas) 0 = word address mode. all memory address counter bits shift down by one bit and the msb of the address counter appears on the lsb 1 = byte address mode bit 5 address wrap is useful in implementing cga mode. (aw) 0 = in word address mode, memory address counter bit 13 appears on the memory address output signal of the crt controller and the video memory address wraps around at 16kb. 1 = in word address mode, memory address counter bit 15 appears on the memory address output bit 0 signal of the crtc controller. bit 4 reserved (r) bit 3 word mode select (ws) 76543210 vertical blank end 76543210 hr bas aw r ws hcs ega cga
19 - 20 standard vga registers silicon motion ? , inc. SM731 confidential databook 0 = byte mode addressing is selected and memory address counter is clocked by the character clock input 1 = word mode addressing is selected and memory address counter is clocked by the character clock divided by two. bit 2 horizontal retrace clock select (hcs) 0 = select horizontal retrace clock rate 1 = select horizontal retrace clock rate divided by two. bit 1 ega emulation (ega) 0 = row scan counter bit 1 is replaced by memory address bit 14 during active display time 1 = memory address bit 14 appear son the memory address output bit 14 signal of the crt controller. bit 0 cga emulation (cga) 0 = row scan counter bit 0 is replaced by memory address bit 13 during active display time 1 = memory address bit 13 appears on the memory address output bit 13 signal of the crt controller. crt18: line compare register read/write address: 3?5h, index 18h power-on default: undefined this register is used to implement a split screen function. when the scan line counter value is equal to the content of this register, the memory address counter is cleared to 0. bit 7:0 line compare register this value = number of scan lines at which the screen is split into screen 1 and screen 2. crt22: graphics controller data latches readback register read only address: 3?5h, index 22h power-on default: undefined this register is used to read the cpu latches in the graphics controller. bit 7:0 graphics controller cpu data latches bits 1-0 of gr4 select the latch number n (3-0) of the cpu latch. crt24: attribute controller toggle readback register read only address: 3?5h, index 24h 76543210 line compare register 76543210 graphics controller cpu data latches
standard vga registers 19 - 21 silicon motion ? , inc. SM731 confidential databook power-on default: undefined this register is used to provide acce ss to the attribute controller toggle. bit 7 attribute controller index select (acs) 0 = the attribute controller reads or writes an index value on the next access 1 = the attribute controller reads or writes a data value on the next access bit 6:0 reserved crt26: attribute controller index readback register read only address: 3?5h, index 26h power-on default: undefined this register is used to provide acce ss to the attribute controller index. bit 7:6 reserved bit 5 video enable status (ves) this bit provides status of the video display enable bit in attribute controller (3c0h) index bit 5. bit 4:0 attribute controller index this value is the attribute controller index data at 3c0h. graphics controller registers the graphics controller registers are locat ed at a two byte i/o address space. the registers are accessed by first writing an index to 3ceh and followed by writing a data to 3cfh. grxx: graphics controller index register read/write address: 3ceh power-on default: undefined this register is loaded with a binary value that indexes the graphics controller register where data is to be accessed. 76543210 acs reserved 76543210 reserved ves attribute controller index
19 - 22 standard vga registers silicon motion ? , inc. SM731 confidential databook bit 7:4 reserved bit 3:0 graphics controller address index these bits specify the graphics controller register to be addressed. its value is programmed in hexadecimal. grx00: set/reset register read/write address: 3cfh, index: 00h power-on default: undefined this register represents the value written to all 8-bits of the corresponding memory planes when cpu executes a memory write in write mode 0. bit 7:4 reserved bit 3:0 set/reset plane3:0 in write mode 0, the set/reset data can be enabled on the corresponding bit of the bit of the enable set/ reset data register. these bits become the color value for cpu memory write operations. grx01: enable set/reset register read/write address: 3cfh, index: 01h. power-on default: undefined this register enable the set/reset register in write mode 0. bit 7:4 reserved bit 3:0 enable set/reset plane3:0 in write mode 0, the enable set/reset bits allow writing to the corresponding planes with the data in set/ reset register. a logical 0 disables the set/reset data in a plane, and that plane is written with the value of cpu write data. 76543210 reserved graphics controller 76543210 reserved set/reset plane 76543210 reserved enable set/reset plane
standard vga registers 19 - 23 silicon motion ? , inc. SM731 confidential databook grx02: color compare register read/write address: 3cfh index: 02h. power-on default: undefined this register is to used to compare with the cpu memory read data. this register works in conjunction with the color don't care register. bit 7:4 reserved bit 3:0 color compare plane [3:0] these bits represent the reference color used to co mpare each pixel in corresponding plane. a logical 1 is returned in each plane bit position when color matches. grx03: data rotate/rop register read/write address: 3cfhindex: 03h. power-on default: undefined this register is to used to control rotation and raster operations. bit 7:5 reserved bit 4:3 raster operations select (ros) 00 = no operation 01 = logical and with latched data 10 = logical or with latched data 11 = logical xor with latched data bit 2:0 rotate count these bits specifies the number of bit positions of rotation to the right. data written by the cpu is rotated in write mode 0. to write non-rotated data, the cpu must present a count with 0. grx04: read plane select register read/write address: 3cfhindex: 04h. power-on default: undefined this register is selects which memory plane the cpu data is r eading from in read mode 0. this register has no effect on the color compare read mode (read mode 1). in odd/even mode, bit 0 is ignored. 76543210 reserved color compare plane 76543210 reserved ros rotate count
19 - 24 standard vga registers silicon motion ? , inc. SM731 confidential databook bit 7:2 reserved bit 1:0 read plane select is as follows: 00 = plane 0 01 = plane 1 10 = plane 2 11 = plane 3 grx05: graphics mode register read/write address: 3cfhindex: 05h. power-on default: undefined this register is selects which memory plane the cpu data is r eading from in read mode 0. this register has no effect on the color compare read mode (read mode 1). in odd/even mode, bit 0 is ignored. bit 7 reserved (r) bit 6 256 color shift mode select (cs) 0 = enable bit 5 of this register to control loading of the shift registers. 1 = the shift registers are loaded in a manner that support the 256 color mode. bit 5 odd/even shift mode select (oes) 0 = normal shift mode 1 = the video shift registers are directed to format th e serial data stream with even numbered bits from both planes on the even numbered planes and odd nu mbered bits from both planes on the odd planes. bit 4 odd/even addressing select (oea) 0 = normal addressing 1 = cga odd/even addressing mode is selected. even cpu addresses access plane 0 and 2, while odd cpu addresses access plane 1 and 3. bit 3 enable read compare (erc) 0 = system read data from memory planes selected by read map select register (3cfh index 04h). this is called read mode 0. 1 = system read the results of logical comparison betw een the data in 4 memory planes selected by the color don't care register and the color compare register. the results is a 1 for a match and 0 for a mismatch on each pixel. this is called read mode 1. bit 2 reserved (r) 76543210 reserved read plane 76543210 r cs oes oea erc r writing mode
standard vga registers 19 - 25 silicon motion ? , inc. SM731 confidential databook bit 1:0 write mode select 00 = write mode 0. each of four video planes is written with cpu data rotated by the number of counts in rotate register. if set/reset register is enabled fo r any of the four planes, the corresponding planes is written with the data stored in the set/reset register. 01 = write mode 1. each of four video planes is written with cpu data in the processor latches. these latches are loaded during previous cpu read operations . raster operation, rotate count, set/reset data, enable set/reset data and bit mask registers are ignored. 10 = write mode 2. video planes [3:0] are written with the value of cpu write data [3:0]. the 32-bit output from the four planes is then operated on by the bit mask register and the resulting data are written into the four planes. the set/reset, enable set/reset and rotate count registers are ignored. 11 = write mode 3. each of the four video planes is written with 8-bit of the color value in the set/reset register for the corresponding plane. the bit-position-enable field is formed with the logical and of the bit mask register and rotated cpu data. the enable set/reset register is ignored. grx06: graphics miscellaneous register read/write address: 3cfhindex: 06h. power-on default: undefined this register controls video memory addressing. bit 7:4 reserved bit 3:2 memory map mode. these bits control the address mapping of video memory into the cpu address space. 00 = a0000h to bffffh (128kb) 01 = a0000h to affffh (64kb) 10 = b0000h to b7fffh (32kb) 11 = b8000h to bffffh (32kb) bit 1 odd/even mode select (oes) 0 = cpu address bit a0 is the memory address bit ma0 1 = cpu address a0 is replaced by a higher order addr ess bit. a0 is then used to select odd or even maps. a0=0, selects map 2 or 0; a0 = 1, select map 3 or 1. bit 0 graphics mode select (gms) 0 = select text mode 1 = select graphics mode grx07: color don't care plane register read/write address: 3cfhindex: 07h. power-on default: undefined 76543210 reserved memory map oes gms
19 - 26 standard vga registers silicon motion ? , inc. SM731 confidential databook this register controls whether the corresponding bit of the color compare register, grx02, is to be ignored or used for color comparison. this register is used with grx02 for read mode 1 accesses. bit 7:4 reserved bit 3:0 compare plane select 0 = the corresponding color plane becomes a don' t care plane when the cpu read from the video memory is performed in read mode 1. 1 = the corresponding color plane is used for colo r comparison with the data in the color compare register, grx02. grx08: bit mask register read/write address: 3cfh, index: 08h. power-on default: undefined this register controls bit mask operations which applies simultaneously to all four maps. the data written into memory in this case is the data which was read in the previous cycle, and was stored in the processor latches. any bit programmed to 1 allows unimpeded writes to the corresponding bits in the plane. bit 7:0 bit mask 0 = corresponding bit of each plane in memory is set to the corresponding bit in the processor latches. 1 = corresponding bit of each plane in memory is set as specified by other conditions. attribute controller registers the attribute controller registers are located at the same byte i/o address for writing address and data. the attribute index register has an internal flip-flop rather than an input bit to control the selection of the address and data registers. reading the input status register 1 at port 3?ah clears the flip-flop and selects the addres s register, which is read at address 3c1h and written at address 3c0h. once the address register has been loaded with an index, the next write operation to 3c0h loads the data register. the flip-flop toggles between the ad dress and the data register after every write to address 3c0h, but does not toggle for reads from address 3c1h. furthermor e, the attribute controller inde x register is read at 3c0h, and the attribute controller data register is read at address 3c1h. atrx: attribute controller index register read/write address: 3c0h power-on default: undefined this register is loaded with a binary value that indexes the attribute controller register where data is to be accessed. 76543210 reserved compare plane select 76543210 bit mask
standard vga registers 19 - 27 silicon motion ? , inc. SM731 confidential databook bit 7:6 reserved bit 5 palette address source (pas) 0 = disable internal color palette outputs and video outputs to allow cpu access to color palette registers 1 = enable internal color palette and normal video translation. bit 4:0 attribute controller address a binary value that points to the attribute controller register where data is to be written. atr00-0f: palette register read/write address: 3c1h/3c0h, index 00h - 0fh. power-on default: undefined this register is loaded with a binary value that indexes the attribute controller register where data is to be accessed. bit 7:6 reserved bit 5:0 palette colors 0 = corresponding pixel color is de-selected 1 = corresponding pixel color is enabled atr10: attribute mode control register read/write address: 3c1h/3c0h, index: 10h. power-on default: 00h this register controls the attribute mode of the display function. bit 7 vid5, vid4 select (vid) 0 = vid5 and vid4 palette register outputs are selected 1 = color select register port 3c1h/3c0h, index 14h, bit 1 and bit 0 are selected for outputs. bit 6 256 color select (cs) 0 = disable 256 color mode pixel width. pclk rate = internal dot clock rate. 76543210 reserved pas attribute controller address 76543210 reserved palette colors 76543210 vid cs ppe r bis lgc mce tgm
19 - 28 standard vga registers silicon motion ? , inc. SM731 confidential databook 1 = enable 256 color mode pixel width. pclk rate = internal dot clock rate / 2 bit 5 pixel panning enable (ppe) 0 = line compare will have no effect on the output of the pixel panning register 1 = forces the output of the pixel panning register to 0 after matching line compare until vsync is active bit 4 reserved (r) bit 3 blinking and intensity select (bis) 0 = select background intensity from the text attribute byte. 1 = select blink attribute in text modes bit 2 line graphics character enable (lgc) 0 = forces the ninth dot to be the same color as the background in line graphics character codes. 1 = enable special line graphics character codes. bit 1 mono/color emulation (mce) 0 = select color display text attributes 1 = select monochrome display text attributes bit 0 text /graphics mode select (tgm) 0 = select text attribute control mode 1 = select graphics control mode atr11: overscan color register read/write address: 3c1h/3c0h, index: 11h. power-on default: 00h this register controls the overscan or border color. this register will be locked if crt3c register (3?5h, index 3ch) bit 5 is set to 1. please refer to crt3c register for details. bit 7:0 overscan color register determines the oversca n or border color displayed on the crt screen. atr12: color plane enable register read/write address: 3c1h/3c0h, index: 12h. power-on default: 00h this register enables the respective video memory color plan 0- 3 and selects the video color outputs to be read back in the display status. 76543210 overscan color register 76543210 reserved video satus color plane enable
standard vga registers 19 - 29 silicon motion ? , inc. SM731 confidential databook bit 7:6 reserved bit 5:4 video status multiplexer. these bits select two out of the 8 color outputs which can be read by the input status register 1 at port 3?ah, bit 5 and bit 4. bit 3:0 color plane enable 0 = disable the corresponding color planes. forces pixel bit to be 0 before it address palette. 1 = enables the corresponding color planes. atr13: horizontal pixel panning register read/write address: 3c1h/3c0h, index: 13h. power-on default: 00h this register specifies the number of pixels to shift the display data horizontally to the left. horizontal pixel panning is available in text and graphics modes. bit 7:4 reserved bit 3:0 horizontal pixel panning. these 4 bits determine the horizontal left shift of the video data in number of pixels. in the 9 pixel/character text mode, the output can be shifted a maximum shift of 8 pixels. in the 8 pixel/character text mode and all graphics modes, except for 256 color mode, a maximum shift of 7 pixels is allowed. in the 256 color mode, bit 0 of this register must be 0 resulting in only 4 panning positions per display byte. the panning is controlled as follows: color plane register input status register 1 bit 5bit 4bit 5bit 4 0 0 vid2 vid0 0 1 vid5 vid4 1 0 vid3 vid1 1 1 vid7 vid7 76543210 reserved horizontal pixel planning bits 3:0 9 pixel/character 8 pixel/character 256 color modes 0000 1 0 0 0001 2 1 - 0010 3 2 1 0011 4 3 - 0100 5 4 2 0101 6 5 - 0110 7 6 3
19 - 30 standard vga registers silicon motion ? , inc. SM731 confidential databook atr14: color select register read/write address: 3c1h/3c0h, index: 14h. power-on default: 00h this register specifies the high-order bits of video output when pixel padding is enable/disabled for 256 color modes. bit 7:4 reserved bit 3:2 select color 7 and color 6 (sc7/6) these are the two most significant bits of the 8 bi ts color value for video dac. these are normally used in all modes except 256 color modes. bit 1:0 select color 5 and color 4 (sc5/4) these bits can be substituted for vid5 and vid4 from the palette registers to form the 8-bit color value for video dac. ramdac registers the section describes the ramdac register s. special programming sequences are used to read or write data to and from the ramdac. writing data to dac: write the color code to dac write address register at 3c8h. three bytes: red, green, blue values are written into dac data register at 3c9h. following the third write, the values are transferred to color lookup table.  the dac write address register is auto incremented by 1. reading data from dac:  write the color code to dac read address register at 3c7h.  three bytes: red, green, blue values are read from the dac data register at 3c9h. 3c6: dac mask register read/write address: 3c6h power-on default: undefined this register is the pixel read mask register to select pixel video output. 0111 8 7 - 1000 0 - - 76543210 reserved sc7/6 sc5/4
standard vga registers 19 - 31 silicon motion ? , inc. SM731 confidential databook bit 7:0 dac address mask this field is the pixel mask for palette dac. when a bit in this field is programmed to 0, the corresponding bit in the pixel data is ignored in looking up an entry i the color lookup table. this register is initialized to ffh by the bios during a video mode set. 3c7w: dac address read register write only address: 3c7h power-on default: undefined this register contains the pointer to one of the 256 palette data registers and is used wh en reading the color palette. a write to this register causes 11b to be driven out to the ramdac output. bit 7:0 dac read address after a color code is written into this register, the chip will identifies that a dac read sequence will occur. a read sequence consists of three consecuti ve byte reads from the ramdac data register at 3c9h. 3c7r: dac status register read only address: 3c7h power-on default: undefined this register specifies the dac status: read or write cycles. bit 7:2 reserved bit 1:0 dac status bits 00 = dac write operation in progress 11 = dac read operation in progress 3c8: dac address write register read/write address: 3c8h power-on default: undefined 76543210 dac address mask 76543210 dac read address 76543210 reserved dac status
19 - 32 standard vga registers silicon motion ? , inc. SM731 confidential databook this register contains the pointer to one of the 256 palette da ta registers and is during a palette load. a write to this regis ter causes 11b to be driven out to the ramdac output. bit 7:0 dac write address after a color code is written into this register, th e chip identifies that a dac write sequence will occur. a write sequence consists of three consecutive byte reads from the ramdac data register at 3c9h. 3c9: dac data register read/write address: 3c9h power-on default: undefined this register is the data port to read or write the contents of the location in the color lookup table pointed to by the dac read address or the dac write address registers. an access to this register will cause 01b to be driven to ramdac outputs. bit 7:0 dac read/write data these read/write register bits store the pixel data for the palette dac 76543210 dac write address 76543210 dac read/write data
extended smi io mapped registers 20 - 1 silicon motion ? , inc. SM731 confidential databook chapter 20: extended smi io mapped registers table 23: extended smi io mapped registers quick reference summary of registers page system control registers scr15: pci miscellaneous control register 20 - 5 scr16: status for drawing engine and video processor 20 - 6 scr17: general graphics command register 1 20 - 7 scr18: general graphics command register 2 20 - 8 scr19: interrupt enable and mask i 20 - 9 scr1a: interrupt status 20 - 10 scr1b: interrupt status enable and mask ii 20 - 10 scr1c: interrupt status 20 - 10 scr1f: interrupt mask and hardware interrupt enable 20 - 12 scr24: reserved 20 - 12 scr25: agp pll control 20 - 13 power down control registers pdr20: power down control for memory, flat panel, pll, and video port 20 - 14 pdr21: functional blocks power down control 20 - 15 pdr22: dpms control select 20 - 16 pdr23: dynamic power management control register 20 - 17 pdr24: power down register select 20 - 18 memory control registers mcr60: memory control 20 - 18 mcr61: memory bank address high 20 - 19 mcr62: memory type and timing control 20 - 19 mcr76: memory type and timing control 20 - 19 clock control registers ccr63: memory controller clock numerator register 20 - 21 ccr64: memory controller clock denominator register 20 - 21 ccr65: tv encoder control register 20 - 22 ccr66: ram control and function on/off register 20 - 23
20 - 2 extended smi io mapped registers silicon motion ? , inc. SM731 confidential databook ccr67: for test purpose only 20 - 23 ccr68: clock control 1 20 - 24 ccr69: clock control 2 20 - 25 ccr6a: mclk numerator register 20 - 26 ccr6b: mclk denominator register 20 - 26 ccr6c: vclk numerator register 20 - 27 ccr6d: vclk denominator register 20 - 27 ccr6e: panel clock numerator register 20 - 28 ccr6f: panel clock denominator register 20 - 28 ccr78: scratch register i 20 - 28 ccr79: scratch register 2 20 - 29 ccr7a-ccr7c: tv and ramdac testing power 20 - 29 ccr7d: control registers for tv and ramdac testing 20 - 29 ccr94: mck pll numerator adjustment 20 - 30 ccr95: mck2 pll numerator adjustment 20 - 30 ccr96: mck pll numerator adjustment 2 20 - 30 ccr97: mck2 pll numerator adjustment 2 20 - 31 ccr98: mck pll numerator adjustment 3 20 - 31 ccr99: mck2 pll numerator adjustment 3 20 - 31 ccr9a: mck pll numerator adjustment 4 20 - 31 ccr9b: mck2 pll numerator adjustment 4 20 - 32 ccr9c: mck pll numerator adjustment 5 20 - 32 ccr9d: mck2 pll numerator adjustment 5 20 - 32 ccr9e: pll post divider control 20 - 33 general purpose registers gpr70: scratch pad register 1 20 - 33 gpr71: scratch pad register 2 20 - 34 gpr72: user defined register 1 for ddc2/ i2c 20 - 34 gpr73: user defined register 2 20 - 35 gpr74: scratch pad register 3 20 - 36 gpr75: scratch pad register 4 20 - 36 pop-up icon and hardware cursor registers phr80: pop-up icon and hardware cursor pattern location low 20 - 36 phr81: hardware cursor enable & pi/hwc pattern location high 20 - 37 pop-up icon registers pop82: pop-up icon control 20 - 37 pop83: reserved 20 - 37 summary of registers (continued) page
extended smi io mapped registers 20 - 3 silicon motion ? , inc. SM731 confidential databook pop84: pop-up icon color 1 20 - 38 pop85: pop-up icon color 2 20 - 38 pop86: pop-up icon color 3 20 - 38 pop90: pop-up icon start x - low 20 - 39 pop91: pop-up icon start x - high 20 - 39 pop92: pop-up icon start y - low 20 - 39 pop93: pop-up icon start y - high 20 - 39 hardware cursor registers hcr88: hardware cursor upper left x position - low 20 - 40 hcr89: hardware cursor upper left x position- high 20 - 40 hcr8a: hardware cursor upper left y position - low 20 - 41 hcr8b: hardware cursor upper left y position - high 20 - 41 hcr8c: hardware cursor foreground color 20 - 41 hcr8d: hardware cursor background color 20 - 42 extended crt control registers crt30: crtc overflow and interlace mode enable 20 - 42 crt31: interlace retrace 20 - 43 crt32: tv vertical display enable start 20 - 43 crt33: tv vertical display enable end - high 20 - 43 crt34: tv vertical display enable end - low 20 - 44 crt35: vertical screen expansion dda control constant - low 20 - 44 crt36: vertical screen expansion dda control constant - high 20 - 44 crt37: hardware/vga test selection/display control 20 - 45 crt38: extra horizontal timing control 20 - 45 crt39: scratch register 20 - 46 crt3a: tv total timing control for the internal tv encoder 20 - 46 crt3b: miscellaneous lock register i 20 - 47 crt3c: miscellaneous lock register ii 20 - 47 crt3d scratch register bits 20 - 48 crt3e: scratch register bits 20 - 48 crt3f: scratch register bits 20 - 48 crt9e: expansion/centering control register 2 20 - 48 crt9f: expansion/center control register 1 20 - 49 crt90-9b vertical dda look up table & crta0-a5: vertical centering offset look up ta bl e 20 - 50 crta0-a5: vertical centering offset look up table 20 - 51 crta6: vertical centering offset register 20 - 51 summary of registers (continued) page
20 - 4 extended smi io mapped registers silicon motion ? , inc. SM731 confidential databook crta7: horizontal centering offset register 20 - 52 crta8-ad: horizontal screen centering look up table 20 - 52 shadow vga registers svr40: shadow vga horizontal total 20 - 53 svr41: shadow vga horizontal blank start 20 - 53 svr42: shadow vga horizontal blank end 20 - 54 svr43: shadow vga horizontal retrace start 20 - 54 svr44: shadow vga horizontal retrace end 20 - 54 svr45: shadow vga vertical total 20 - 55 svr46: shadow vga vertical blank start 20 - 55 svr47: shadow vga vertical blank end 20 - 55 svr48: shadow vga vertical retrace start 20 - 55 svr49: shadow vga vertical retrace end 20 - 56 svr4a: shadow vga vertical overflow 20 - 56 svr4b: shadow vga maximum scan line 20 - 57 svr4c: shadow vga horizontal display end 20 - 57 svr4d: shadow vga vertical display end 20 - 57 summary of registers (continued) page
extended smi io mapped registers 20 - 5 silicon motion ? , inc. SM731 confidential databook extended smi registers this chapter describes the extended smi registers including:  system control registers  power down control register  memory control registers  clock control registers  general purpose registers  popup-icon and hardware cursor registers  extended crt registers  shadow vga registers all extended smi registers are accessed through 3c3h, 3c5h, or 3?5h address. (? = b for monochrome mode and d for color mode) or through their mmi0 location. in order to acces s extended smi registers, one must unlock the extended smi register by writing 010xxxxxb to lock register (3c3h). the name of the register consists of the index which the register resides in. for example, scr10 can be accessed through index 10h of 3c5h. system control registers all system control registers are controlled by pci system clock, rather than memory clock (mclk) or video clock (vclk). during SM731 power down (when mclk and vclk are shutdown), the system control registers can still be accessed through pci bus. scr15: pci miscellaneous control register read only address: 3c5h, index: 15h power-on default: 00h this register defines the various pci control registers. bit 7 pci burst read enable (bre) 0 = disable 1 = enable. scr17 bit 5 needs to be set to 1 in order for this bit to take effect. for example, if scr17 bit 5 = 0, even this bit is set to 1, pci burst read will not be enabled. bit 6 abort 3d engine (abort) 0 = 3d engine normal operation 1 = abort 3d engine activities bit 5 software abort drawing engine enable (sde) 0 = normal 1 = enable. this bit has no effect unless bit 4 is set to 1. bit 4 drawing engine abort enable (dea) 0 = normal 1 = enable 76543210 bre abort sde dea pci bios xfer
20 - 6 extended smi io mapped registers silicon motion ? , inc. SM731 confidential databook bit 3 pci configuration space: subsystem id lock enable (pci) 0 = disable 1 = enable bit 2 full range for bios access (bios) bit 1:0 # of double word transfer during burst read = for performance tuning purpose 00 = 2 3d-bit double words 01 = 4 3d-bit double words ix = 8 3d-bit double words scr16: status for drawing engine and video processor read only address: 3c5h, index: 16h power-on default: undefined this register specifies status of SM731 including drawing engine status, video processor status, and drawing engine fifo available. bit 7 graphics engine status (ges) 0 = indicate current display frame is using the source starting address 1 = indicate current display frame is not using the source starting address bit 6 video window i status (vwi) 0 = indicate current display frame is using the source starting address 1 = indicate current display frame is not using the source starting address bit 5 video window ii status (vwii) 0 = indicate current display frame is using the source starting address 1 = indicate current display frame is not using the source starting address bit 4 drawing engine is empty and ready (de 0 = drawing engine not empty 1 = drawing engine empty bit 3 2d drawing engine busy status (debs) 0 = drawing engine idle 1 = drawing engine busy bit 2 3d engine busy status (3debs) 0 = 3d engine idle 1 = 3d engine busy bit 1 vpr53_7 (vpr) subpicture status 76543210 ges vwi vwii de debs 3debs vpr vprcb
extended smi io mapped registers 20 - 7 silicon motion ? , inc. SM731 confidential databook 0 = indicate current display frame is using the source starting address 1 = indicate current display frame is not using the source starting address bit 0 vprcb_7 scr17: general graphics command register 1 read/write address: 3c5h, index: 17h power-on default: 00h this register specifies command controls for memory access disable, pci bus master status, pci bus burst write and burst read enable, big-endian swap mode select, direct 3d data buffer select, memory mapped access enable and bios rom size select. bit 7 memory access disable when drawing engine busy (mad) 0 = normal 1 = disable memory access when drawing engine is busy bit 6 start pci bus master (pci) 0 = stop pci 1 = start pci bit 5 pci burst read and write enable. (pci1) 0 = disable 1 = enable bit 1 memory mapped aperture select (mma) 0 = select banking aperture. no memory mapped registers access allowed. 1 = select memory mapped aperture bit 0 disable latency timer (dlt) 76543210 mad pci pci1 besm direct3d mma dlt bit 4 big endian swap mode select (besm) before [31:24] [23:16] [15:8] [7:0} 0 = big endian with byte swap after [7:0] [15:8] [23:16] [31:24] 1 = big endian with word swap before [31:16] [15:0] bit 3:2 direct3d z-buffer data select after [15:0] 31:16] 00 = normal (use all 32-bit data) 01 = use low word [15:0] 10 = use high word [31:16] 11 = normal (use all 32-bit data)
20 - 8 extended smi io mapped registers silicon motion ? , inc. SM731 confidential databook 0 = normal 1 = disable latency timer count scr18: general graphics command register 2 read/write address: 3c5h, index: 18h power-on default: 00h this register specifies command control for aperture select, graphics modes select, 32/64 memory data path select and linear addressing mode enable. bit 7 select ~clkrun or activity (sclk) 0 = select ~clkrun as input for pin 161 1 = select acitivity as output for pin 161 bit 6 enable ~clkrun function (eclk) 0 = disable 1 = enable bit 5 aperture select. this bit is only valid in linear memory mode (bit 0 = 1) (as) 0 = select dual aperture. allow 0a0000h-0a ffffh and linear aperture to coexist. 1 = select single aperture. only linear aperture can be used. bit 4:3 graphics modes select for memory access 00 = standard vga mode. the memory access only uses the lower 32-bit of the 64-bit internal memory bus. the memory address wraps after 256 kb. 01 = vesa super vga 16 color (4-bit) mode. the memory access only uses the low 32-bit of the 64- bit internal memory bus. the memory address does not wrap after 256 kb. 1x = extended packed pixel graphics modes (8 /16/24/32-bit). the memo ry access always use the internal 64-bit memory bus. bit 2 32/64 memory data path select. this bit is only valid in vga or vesa super vga 16 color modes (bit 4 of this register = 0) (mdp) 0 = cpu access vga memory. all host memory access goes through vga aperture: 0a0000h - 0bffffh (controlled by 3cfh index 6 bit [3:2]). th e memory access only uses the low 32-bit of the 64- bit memory bus. 1 = cpu access graphics memory. all host memory access does not goes through vga aperture. this bit is used to allow 64-bit memory access even in vga or super vga 16 color modes. for example, when programming pop-up icon in vga mode or vesa super vga 16 color mode, one must set bit 2 = 1 and bit 4 = 0 of this register, in order to access full range of the display memory. bit 1 enable repeat hardware rotation blt function (erh) 0 = disable 1 = enable bit 0 linear memory mode enable (lmm) 76543210 sclk eclk as graphics mode mdp erh lmm
extended smi io mapped registers 20 - 9 silicon motion ? , inc. SM731 confidential databook 0 = disable. nonlinear addressing (banking) mode is selected, and mcr61 register will be used for memory bank select. memory will be accessed according to 3cf index 6 bit [3:2]: 3cf.6 bit [3:2] memory range 00 0a0000-0bffff 01 0a0000-0affff 10 0b0000-0b7000 11 0b8000-0bffff 1 = enable. linear memory mode is selected, an d memory will be accessed according to the pci base address register. scr19: interrupt enable and mask i read/write address: 3c5h, index: 19h power-on default: 00h this register specifies interrupt enables and interrupt masks for pci master, zoom video port, and drawing engine. each interrupt mask will block out its particular interrupt when the interrupt mask is enabled. when the interrupt mask is disabled, the corresponding interrupt will be generated when its particular interrupt is enabled. bit 7 interrupt enable for vga (ievga) bit 6 panel vertical blanking interrupet (pvbi) 0= disable 1 = enable bit 5 interrupt enable for zoom video port (iezvp) 0 = disable 1 = enable bit 4 interrupt enable for 2d/3d drawing engine (iede) 0 = disable 1 = enable bit 3 reserved bit 2 panel vertical blanking interrupt mask (pvbim) 0 = disable 1 = enable bit 1 interrupt mask for zoom video port (imzvp) 0 = disable 1 = enable bit 0 interrupt mask for 2d/3d drawing engine (imde) 0 = disable 1 = enable 76543210 ievga pvbi iezvp iede r pvbim imzvp imde
20 - 10 extended smi io mapped registers silicon motion ? , inc. SM731 confidential databook scr1a: interrupt status read only address: 3c5h, index: 1ah power-on default: undefined this register specifies interrupt status of drawing engine , video port, pci master, and vga. the interrupt enable and mask bits for these interrupts are located in scr19 register , with the exception of vga's enable and mask bits which reside within the vga block. bit 7 icmd interrupt status (icmd) 0 = no interrupt 1 = icmd interrupt is detected bit 6 idct interrupt status (idct) bit 5 3d texture engine interrupt status (3d te) 0 = no interrupt 1 = 3d texture engine interrupt detected bit 4 vga interrupt status. vga's interrupt enable and mask bits are in the vga block. (vga) 0 = no interrupt 1 = vga interrupt is detected bit 3 host memory control interrupt status (hmcis) 0 = no interrupt 1 = master control bit 2 panel vertical blank interrupt status (pvbi) 0 = no interrupt detected 1 = interrupt detected bit 1 zoom video port interrupt status (zvp) 0 = no interrupt 1 = zoom video port interrupt is detected bit 0 2d/3d drawing engine interrupt status (dei) 0 = no interrupt 1 = drawing engine interrupt is detected scr1b: interrupt status enable and mask ii read only: address: 3c5h, index: 1bh power-on default: 00h 76543210 icmd idct 3d te vga hmcis pvbi zvp dei
extended smi io mapped registers 20 - 11 silicon motion ? , inc. SM731 confidential databook bit 7 icmd interrupt enable (icmdie) 0 = disable icmd interrupt (hardware interrupt to system) 1 = enable icmd interrupt (hardware interrupt to system) bit 6 idct interrupt enable (idctie) 0 = disable idct interrupt (hardware interrupt to system) 1 = enable idct interrupt (hardware interrupt to system) bit 5 text 3d interrupt enable (texture) 0 = disable text 3d interrupt (hardware interrupt to system) 1 = enable text 3d interrupt (hardware interrupt to system) bit 4 host master control interrupt enable (hmcie) 0 = disable host master interrupt (hardware interrupt to system) 1 = enable host master interrupt (hardware interrupt to system) bit 3 icmd interrupt mask (icmdim) 0 = allow icmd interrupt signal to be latched into interrupt register 1 = will not allow icmd interrupt signal to be into interrupt register bit 2 idct interrupt mask (idctim) 0 = allow idct interrupt signal to be latched into interrupt register 1 = will not allow idct interrupt signal to be into interrupt register bit 1 texture (texture) 0 = allow texture interrupt signal to be latched into interrupt register 1 = will not allow texture interrupt signal to be into interrupt register bit 0 host control interrupt mask master (hcimm) 0 = allow host control interrupt signal to be latched into interrupt register 1 = will not allow host control interrupt signal to be into interrupt register scr1c: interrupt status read only: address: 3c5h, index: 1ch power-on default: 00h bit 7:4 reserved bit 3 usr3 interrupt status 76543210 icmdie idctie texture hmcie icmdim idctim texture hmimm 76543210 reserved usr3 usr2 acon r
20 - 12 extended smi io mapped registers silicon motion ? , inc. SM731 confidential databook bit 2 usr2 interrupt status bit 1 ?acon? pin status change interrupt status bit 0 reserved scr1f: interrupt mask and hardware interrupt enable read only: address: 3c5h, index: 1fh power-on default: 00h bit 7 usr3 to enable system hardware interrupt 0 = disable usr3 pin as interrupt (default) 1 = enable usr3 pin as interrupt input bit 6 usr2 to enable system hardware interrupt 0 = disable usr3 pin as interrupt (default) 1 = enable usr3 pin as interrupt input bit 5 ?acon? pin interrupt 0 = disable ?acon? pin interrupt 1 = enable ?acon? pin interrupt bit 4 reserved bit 3 usr3 interrupt mask bit 2 usr2 interrupt mask bit 1 ?acon? pin status change interrupt 0 = no mask for ?acon? pin status change interrupt 1 = mask out for ?acon? pin status change interrupt bit 0 reserved scr24: reserved read only: address: 3c5h, index: 24h power-on default: 00h 76543210 usr3 usr2 api r usr3im usr2im aps r 76543210 reserved default reserved
extended smi io mapped registers 20 - 13 silicon motion ? , inc. SM731 confidential databook bit 7:6 reserved bit 5:4 11 = default bit 3:0 reserved scr25: agp pll control read/write address: 3c5h, index: 25h power-on default: 00h this register controls the agp4x clock bit 7:6 programmable agp4x clock delay 00: delay 0 ns (default) 01: delay 0.3 ns 10: delay 0.6 ns 11: delay 0.9 ns bit 5:4 4x pll band width control (pll?s bw_cntrl [1:0]) 00: loop bw = 1 mhz (default) 01: loop bw = 2 mhz 11: loop bw = 3 mhz 10: reserved bit 3 leading/lagging control (pll?s select input) 0: pll output clock phase lagging input by ~500ps (default) 1: pll output clock phase leading input by ~500 ps bit 2 bypass pll (pll?s test input) 0: pll in normal operation output (default) 1: pll in bypass mode, clk_out direct from clk_in bit 1 power down the agp pll (pll?s power down input) 0: pll power enable (default) 1: pll in power down mode bit 0 use xor 4x clock (this is a mux selection outside the pll) 0: 4x clock from pll (default) 1: 4x clock from xor scr26: agp 2x/4x control read/write address: 3c5h, index: 26h power-on default: 00h 76543210 clock delay band width lc bp pd xor
20 - 14 extended smi io mapped registers silicon motion ? , inc. SM731 confidential databook this register is for controlling the voltage reference of the pad. bit 7:6 reserved bit 5 this bit effects csr54_[1] read back status 0 = csr54_[1] read back 1 (agp2x capable) 1 = csr54_[1] read back 0 (not agp2x capable) bit 4 this bit effect csr54_[0] read back status 0 = csr54_[0] read back 1 (agp1x capable) 1 = csr54_[0] read back 0 (not agp1x capable) bit 3 this bit default to 0 is used for hardware adjustment purposes. generally, for 3.3v agp2x systems this bit is set to 0. for 1.5v agp4x systems this bit is set to 1. 0 = select hvreg to control adstb pad 1 = select adstbn for differential pad configurations bit 2:0 voltage reference control for pciclk pad 000 = 00000001: select hvref (40%*agp3.3v=1.32v or 50%*agp1.5v=.75v) (default) 001 = 00000010: select 10% of vddq (3.3v) = .33v 010 = 00000100: select 15% of vddq (3.3v) = .495v 011 = 00001000: select 20% of vddq (3.3v) = .66v 100 = 00010000: select 25% of vddq (3.3v) = .825v 101 = 00100000: select 30% of vddq (3.3v) = .99v 110 = 01000000: select 35% of vddq (3.3v) = 1.155v 111 = 10000000: select 40% of vddq (3.3v) = 1.32v power down control registers the power down control registers are controlled by system cl ock only. the power down control registers can still be read or written by cpu even when internal pll is off. pdr20: power down control for memory, flat panel, pll, and video port read/write address: 3c5h, index: 20h power-on default: 04h this register defines the different power down control for memory, flat panel interface, pll, and video port. this register can still be read or written by cpu even when pll is off. bit 7 sleep mode 76543210 reserved read back ha voltage reference 76543210 sm r pll post divide lvds vpo fpi dmi
extended smi io mapped registers 20 - 15 silicon motion ? , inc. SM731 confidential databook 0 = sleep mode disable 1 = enable bit 6 reserved bit 5:4 pll post divider control 00 = all the pll post dividers disabled 01 = all the pll post dividers enabled each pll post divider is controlled by ccr9e [7:0] respectively 1x = the pll post dividers are enabled only if sleep or standby are active each pll post divider is controlled by ccr9e [7:0] respectively bit 3 tri-state lvdsclk output pin. when ~excken = 0, pin 159 (mckin) becomes an input pin. when ~excken = 1, pin 159 (lvdsclk) becomes an output pin. this register is only valid when ~excken = 1. this bit is used to test the silicon. (lvds) 0 = enable lvdsclk output pin 1 = tri-state lvdsclk output pin bit 2 tri-state video port output. when this bit = 0, 20-bit outputs (r[7:2], g[7:2], b[7:2], blank, and pclk) will be driven out. when video capture is enabled (cpr00 [0] = 1), video port output will be tri-stated automatically, except for blank/tvclk output pin. this bit is used to test the silicon. (vpo) 0 = enable output pins 1 = tri-state output pins (default) bit 1 tri-state flat panel interface output pins. this bit is used to test the silicon (fpi) 0 = enable output pins 1 = tri-state output pins bit 0 tri-state display memory interface output pins. this b it can also be used to isolate SM731 from display memory. all display memory interface pins: control sign als, output clock, data bus and address bus are tri-stated. this bit is used to test the silicon. (dmi) 0 = enable display memory interface output pins 1 = tri-state display memory interface output pins pdr21: functional blocks power down control read/write address: 3c5h, index: 21h power-on default: ha0h this register is designed to achieve optimum power saving in operation mode. special clock drivers are built-in to control major functional blocks independently. this power saving feature will not affect the graphics and video performance, or lcd display quality. this register could be read or written by cpu even when pll is off. bit 7 disable 135 mhz dac (mhz) 0 = enable dac 76543210 mhz plls fbwo pvc ppr zvp de vp
20 - 16 extended smi io mapped registers silicon motion ? , inc. SM731 confidential databook 1 = disable dac bit 6 if ?pwdown? pin is pulled low (deep sleep mode) then this bit controls all the internal plls 0 = enable plls 1 = disable plls bit 5 disable lcd frame buffer write operation. this bit is used to shut-down the (fbwo) 64 x 8 lcd write fifo and remove the display memory bus request for lcd frame buffer write from arbitration control. this bit needs to be set to "1" in dual view mode -- displaying different graphics data on crt (or tv) and lcd. this bit should be set to "1" when lcd display is not enabled or when tft is selected in standard refresh mode in order to obtain optimum power saving. 0 = enable lcd frame buffer write 1 = disable lcd frame buffer write bit 4 panel video clock (pvc) 0 = enable panel video clock (default) 1 = disable panel video clock (vrclk) bit 3 pprvclk shut off (ppr) 0 = normal 1 = shut off pprvclk. no pixels will be clocked out to the crtdac. bit 2 disable zoom video port. this bit is used when there is no external video source which is connected to the SM731. the SM731 will block input data from external video port, turn off the clock driver of zv port, and remove the zv port display memory bus request from memory controller. (zvp) 0 = enable zoom video port 1 = disable zoom video port bit 1 disable 2d/3d drawing engine. this bit is used to turn-off the 2d/3d drawing engine block. for optimum power saving, this bit should be set to "1" in standard vga mode since 2d/3d drawing engine is not in use. (de) 0 = enable 2d/3d drawing engine 1 = disable 2d/3d drawing engine bit 0 disable video processor. this bit is used to turn-o ff the video processor block which includes graphics fifo, v0fifo, v1fifo, horizontal/vertical color interpolation, yuv-to-rgb conversion, tv flicker reduction, hw pop-up icon, and related control logic. for optimum power saving, this bit could be set to "1" in standard vga mode since video processor is not in use. (vp) 0 = enable video processor 1 = disable video processor pdr22: dpms control select read/write address: 3c5h, index: 22h power-on default: x0h
extended smi io mapped registers 20 - 17 silicon motion ? , inc. SM731 confidential databook bit 7:6 reserved bit 5:4 dpms control bit 3:0 reserved pdr23: dynamic power management control register read/write address: 3c5h, index: 23h power-on default: 00h bit 7 enable dynamic power control register (edpc) 0 = disable 1 = enable bit 6:5 detect memory write/read & io write/read (dm) 00 = detect memory write/read & io write/read & capture enable 01 = detect memory write & io write & capture enable 10 = detect memory writ e/read & capture enable 11 = detect io write/read & capture enable bit 4 reserved (r) bit 3:0 timer control to count number of vsync. if there is no bus activities in a specified period, the power management enters ?idle? mode. 0000 = no bus activity detection 0001 = 64 vsync 0010 = 128 vsync 0011 = 256 vsync 0100 = 512 vsync 0101 = 1k vsync 0110 = 2k vsync 0111 = 4k vsync 7 6543210 reserved dpms control reserved dpms state vsync hsync 00 = normal pulses pulses 01 = standby pulses no pulse 10 = suspend no pulse pulses 11 = off no pulse no pulse 76543210 edpc dm r timer control
20 - 18 extended smi io mapped registers silicon motion ? , inc. SM731 confidential databook 1000 = 8k vsync 1001 = 16k vsync 1010 = 32k vsync 1011 = 64k vsync 1100 = 128k vsync 1101 = 192k vsync 1110 = 256k vsync 1111 = 384k vsync pdr24: power down register select read/write address: 3c5h, index: 24h power-on default: 00h bit 7:1 reserved bit 0 power down mode select (pdms) 0 = vesa compliance power down mode 1 = pci power down spec 1.0 compliance memory control registers mcr60: memory control read/write address: 3c5h, index: 60h power-on default: 00h this register specifies memory control for memory address wrap around, dram refresh, vga to memory burst write, and synchronization. this register also includes ramdac write/read command pulse width select. bit 7 reserved bit 6 block write control (bwc) 0 = block write enabled 1 = block write not enabled (default) bit 5 ramdac write/read command pulse width select (ram) 0 = command pulse is 4 mclk high and 12 mclk low 1 = command pulse is 8 mclk high and 24 mclk low 76543210 reserved (pdms) 76543210 r bwc ram dvga vgaf r ddrr drc
extended smi io mapped registers 20 - 19 silicon motion ? , inc. SM731 confidential databook bit 4 disable vga to memory burst write (dvga) 0 = enable 1 = disable bit 3 vga fifo empty level request select. vga fifo is 8 level deep. (vgaf) 0 = vga fifo request if vga fifo is two level empty 1 = vga fifo request if vga fifo is four level empty bit 2 reserved (r) bit 1 disable dram refresh request (ddrr) 0 = enable 1 = disable bit 0 dram refresh control (drc) 0 = normal dram refresh 1 = force to 1 dram refresh per scan line mcr61: memory bank address high read/write address: 3c5h, index: 61h power-on default: 00h this register specifies the high order memory bank address for non-linear addressing (or banking) mode (scr18 bit 0 = 0). bit 7:0 memory bank address high specifies the high-order address for memory access in non-linear addressing (or banking) mode. the host will take these bits append with address [15:0] to form a 22 bits address (4mbyte). mcr62: memory type and timing control read/write address: 3c5h, index: 62h power-on default: this is a power-on configurable register (by reset) SM731 supports internal memory. this register specifies th e memory type and memory timing control. this register is power-on configurable by md [7:0] of memory data bus. bit 7:6 memory dram size (mds) 00 = 4 mbyte 76543210 memory bank address high 76543210 mds mdc tbwc tbpl impd imr
20 - 20 extended smi io mapped registers silicon motion ? , inc. SM731 confidential databook 01 = 32 mbyte 10 = 16 mbyte 11 = 8 mbyte (default) (power on configuration md [7:6]) bit 5:4 memory dram column size (mdc) 0x = 1k dram column 10 = 512 dram column 11 = 256 dram column (default) (power on configuration md [5:4]) bit 3 tbwc - internal memory block write cycle time (tbwc) 0 = 1 mclk 1 = 2 mclk (default) (power-on configuration md [3]) bit 2 block write to precharge (tbpl) 0 = 4 mclk 1 = 1 mclk (default) (power-on configuration md [2]) bit 1 tras - internal memory active to precharge delay (impd) 0 = 6 mclk 1 = 7 mclk (default) (power-on configuration md [1]) bit 0 trc - internal memory refresh to command delay (imr) 0 = 12 mclk 1 = 10 mclk (default) (power-on configuration md [0]) mcr76: memory type and timing control read/write address: 3c5h, index: 76h power-on default: this is a power-on configurable register (by reset) bit 7 enable internal memory (eim) 0 = reserved 1 = normal (default) (power on configuration md [31]) bit 6 force memory reset (fmr) 0 = force memory reset 1 = normal (default) (power on configuration md [30]) 76543210 eim fmr fdra r mbs r de r
extended smi io mapped registers 20 - 21 silicon motion ? , inc. SM731 confidential databook bit 5 force dram remain in active state (fdra) 0 = force dram in active state 1 = normal (default) (power on configuration md [29]) bit 4 reserved bit 3 memory bank selection (mbs) 0 = 2 bank 1 = 4 bank bit 2 reserved bit 1 dll enable (de) 0 = dll not enabled 1 = dll enabled (default) (power-on configuration md [25]) bit 0 reserved clock control registers ccr63: memory controller clock numerator register read/write address: 3c5h, index: 63h power-on default: 0c this register specifies the 8-bit numerator value of mclk2 pll frequency (mnr). bit 7:0 specify the 8-bit numerator value to calcula te the selected mclk2 pll frequency. ccr64: memory controller clock denominator register read/write address: 3c5h, index: 64h power-on default: 02h this register specifies the 6-bit denominator value of mclk2 pll frequency (mdr). bit 7 divide by 2 post scaler (ps) 0 = normal 76543210 8-bit mclk2 pll 76543210 6-bit mclk2 pll
20 - 22 extended smi io mapped registers silicon motion ? , inc. SM731 confidential databook 1 = post scaler enabler bit 6 vco select 0 = select vco for frequency range 20-120 mhz 1 = select vco for frequency higher than 120 mhz bit 5:0 specify the 6-bit denominator value to calculate the selected mclk frequency. the power-on default of this register is 20h. ccr65: tv encoder control register read/write address: 3c5h, index: 65h power-on default: 00h this register specifies the various tv controls. bit 7 svhs tv enable (svhs) 0 = svhs tv off 1 = svhs tv on bit 6 cvbs tv enable (cvbs) 0 = cvbs tv off 1 = cvbs tv on bit 5 tv encoder enable (tvee) 0 = disable tv encoder (tvclk disable) 1 = enable tv encoder bit 4 enable reduceon (ero) level 2 if activity pin is used. 0 = normal 1 = vdd drop bit 3 color ram read control (crrc) 0 = read from crt color ram 1 = read from lcd color ram bit 2 lvds2 clock polarity control 0 = normal 1 = inverted bit 1 lvds1 clock polarity control 0 = normal 1 = inverted 76543210 svhs cvbs tvee ero crrc lvds2 lvds1 vrck
extended smi io mapped registers 20 - 23 silicon motion ? , inc. SM731 confidential databook bit 0 lcd video clock (vrck) jitter ejection control 0 = no jitter ejection from outside chip 1 = jitter ejection enabled. spnlckout pin output the panel control clock source and spnlckin pin feedback the clock with jitter control. ccr66: ram control and function on/off register read/write address: 3c5h, index: 66h power-on default: 00h bit 7:6 ram write control bits (rwcb1) 0 0 both ram on*~ 10lcd ram off 01crt ram off 1 1 both ram off bit 5:4 ram write control bits (rwcb2) 0 0 write both ram (crt/lcd) 1 0 write crt ram only 01write lcd ram only 1 1 reserve bit 3:2 crt ram 8/6 bits and gamma control 006-bits ram 108-bits ram x 1 gamma correct on bit 1 motion comp enable (mce) 1 = disable mcomp*~ 0 = enable mcomp include mcclk off bit 0 3d draweng enable (dee) 1 = disable 3deng*~ 0 = enable 3deng include 3dmclk and 3dmclkb off ccr67: for test purpose only read/write address: 3c5h, index: 67h power-on default: 00h 76543210 rwcb1 rwcb2 crt ram mce dee 76543210 vsync vsync2 vsync3 pll selection pll testing
20 - 24 extended smi io mapped registers silicon motion ? , inc. SM731 confidential databook bit 7:6 11 = the internal vsync counter increment by toggl e ccr67[5] otherwise the internal vsync counter toggled by vsync from crt control. bit 5 toggle this bit will increment the internal vsync counter if bit [7:6] = 11 (vsync2) bit 4 vsync counter (vsync3) 0 = normal 1 = the vsync counter becomes the shift register for testing purposes bit 3:2 pll selection the following tables illustrate controls for the memory clock, engine clock, crt video clock, and panel video clock. config[37] is the power on memory data[37] configuration bit with default high. config[37] ccr67[3:2] engine clock output memory clock output 1 0 ccr6a/ccr6b ccr63/ccr64* 1 1 ccr6a/ccr6b ccr63/ccr64 x 4** 0 00 ccr6a/ccr6b div 2 ccr6a/ccr6b 0 01 ccr6a/ccr6b div 2 agp4xclk (266mhz) 0 11 ccr6a/ccr6b agp4xclk/2 (133 mhz) 0 10 ccr6a/ccr6b ccr6a/ccr6b pwrconfig[37] crt videoclock panelvideoclock 1 ccr6c/ccr6d ccr6e/ccr6f* 0 ccr6e/ccr6f ccr6e/ccr6f * note: this should be the default setting for normal operation. ** note: when pwrconfig[37] and ccr67[2] = 1 the 4xpll is power on. otherwise it is power off. the ccr67[2] needs to be set to 1, prior ccr67[3] set to 1, or ccr67[3] needs to be set to 0 before ccr67[2] is set to 0. bit 1:0 for pll testing purposes or can be used for external panel link or lvds clock 00 = pprvclk goes to xmck pad 01 = inverted pprvclk goes to xmck pad 10 = vrclk2x goes to xmck pad 11 = inverted vrclk2x goes to xmck pad ccr68: clock control 1 read/write address: 3c5h, index: 68h power-on default: 40h this register is used to select cl ock frequencies and pulse-width control. bit 7:6 select vclk frequency based on the following table (vclkf) 76543210 vclkf iso clk select vclk select mclk
extended smi io mapped registers 20 - 25 silicon motion ? , inc. SM731 confidential databook bit 5 enable iso standard at vga modes. this bit is desi gned to increase the crt screen refresh rate to iso standard at vga modes. this bit is used only when ccr68 bit [7:6] = 00b. (iso) 0 = standard vga frequency which controlled by 3c2h bit [3:2] 1 = iso frequency which selected by 3c2h bit [3:2] bit 4 select 8-dot character clock and disable dot clock di vided by 2 function. this bit is used when lcd or tv is selected (determined by fpr31 [2:0]). when this bit set to "1", the bit 3 and bit 0 setting of vga clocking mode register will be ignored. (clk) 0 = character clock and dot clock are co ntrolled by vga clocking mode register 1 = select 8-dot character clock and non-divided by 2 dot clock bit 3:2 select vclk high pulse width 00 = default value 01 = reduce 1 ns high time 10 = increase 1 ns high time 11 = increase 2 ns high time bit 1:0 select mclk high pulse width 00 = default value 01 = reduce 1 ns high time 10 = increase 1 ns high time 11 = increase 2 ns high time ccr69: clock control 2 read/write address: 3c5h, index: 69h power-on default: 80h this register is used to select virtual refresh clock fr equency, dram refresh clock frequency during sleep mode and standby mode, and hsync & vsync control during sleep mode. bit [7:6] ~excken vclk frequency 00 1 vclk is selected from vga 3c2h register 01 1 vclk is selected from programmable vclk registers: ccr6c and ccr6d 10 1 vclk is selected from 17.734 mhz 11 1 vclk is selected from 14.131818 mhz xx 0 vclk is selected from ckin input ccr68 bit 5 3c2h bit [3:2] vclk frequency 0 00 25.180 mhz 0 01 28.325 mhz 1 00 31.500 mhz 1 01 35.484 mhz
20 - 26 extended smi io mapped registers silicon motion ? , inc. SM731 confidential databook bit 7:6 select the lcd video clock high pulse width. the definition is similar to ccr68 [1:0], except for the lcd video clock. bit 5:4 select mclk2 clock high pulse width. this definition is similar to ccr68 [3:2], except for the mclk2. bit 3 this bit becomes read only for th e read back ac power on states 0 = ac power is off 1 = ac power is on bit 2 select hsync and vsync during sleep mode. (pdr20 bit 7 = 1). this bit is used to support vesa dpms during sleep mode. SM731 will automatically support vesa dpms standby mode during its internal standby mode. (shvsm) bit 1:0 lcd video clock 00 = lcd video clock is controlled by the lcd video clock pll 01 = lcd video clock is from the mclk 10 = lcd video clock is from the mclk, divide by 2 11 = same as bit [1:0] = 00 ccr6a: mclk numerator register read/write address: 3c5h, index: 6ah power-on default: 0ch this register specifies the 8-bit numerator value of mclk frequency (mnr). bit 7:0 specify the 8-bit numerator value to calculate the selected mclk frequency. the power-on default of this register is 0ch. ccr6b: mclk denominator register read/write address: 3c5h, index: 6bh power-on default: 02h 76543210 tvclk tdss lvdsclk dram shvsm select vrclk bit 2 dpms state hsync vsync 0 suspend pulses no pulses 1 off no pulses no pulses 76543210 8-bit mclk
extended smi io mapped registers 20 - 27 silicon motion ? , inc. SM731 confidential databook this register specifies the 6-bit denominator value of mclk frequency (mdr). bit 7 divide by 2 post scalar. 0 = disable 1 = enable bit 6 vco select 0 = select vco for frequency range 20mhz to 120mhz 1 = select vco for frequency higher than120mhz bit 5:0 specify the 6-bit denominator value to calculate the selected mclk frequency. the power-on default of this register is 20h. along with ccr6a, the default frequency is set to 40.27 mhz. ccr6c: vclk numerator register read/write address: 3c5h, index: 6ch power-on default: 04h this register specifies the numerator value of vclk frequency (vnr). bit 7:0 specify the numerator value to calcu late the selected vclk frequency. the power-on default setting of this register is 04h. ccr6d: vclk denominator register read/write address: 3c5h, index: 6dh power-on default: 02h this register specifies the 6-bit denominator. bit 7 divide by 2 post scalar. 0 = disable 1 = enable bit 6 vco select 0 = select vco for frequency range 20mhz to 120mhz 1 = select vco for frequency higher than120mhz 76543210 6-bit mclk 76543210 vclk frequency 76543210 ps vco vclk frequency [6]
20 - 28 extended smi io mapped registers silicon motion ? , inc. SM731 confidential databook bit 5:0 specify the 6-bit denominator value to calculate th e selected vclk frequency. the power-on default setting of this register is 02h. ccr6e: panel clock numerator register read/write address: 3c5h, index: 6eh power-on default: 06h this register specifies the 8-bit numerator value of vclk2 frequency (vrclk). bit 7:0 specify the 8-bit numerator value to calculate the selected vrclk frequency. ccr6f: panel clock denominator register read/write address: 3c5h, index: 6fh power-on default: 02h this register specifies the 6-bit denominator value of vrclk frequency. bit 7 divide by 2 post scalar. 0 = disable 1 = enable bit 6 vco select 0 = select vco for frequency range 20mhz to 120mhz 1 = select vco for frequency higher than120mhz bit 5:0 specify the 6-bit denominator value to calculate the selected vrclk frequency. ccr78: scratch register i read/write address: 3c5h, index: 78h power-on default: xxh bit 7:0 scratch register 76543210 8-bit vrclk frequency 76543210 ps vco 6-bit vrclk frequency 76543210 scratch register
extended smi io mapped registers 20 - 29 silicon motion ? , inc. SM731 confidential databook ccr79: scratch register 2 read/write address: 3c5h, index: 79h power-on default: xxh bit 7:0 scratch register ccr7a-ccr7c: tv and ramdac testing power read/write address: 3c5h, index: 7ah-7ch power-on default: 00h bit 7:0 tv and ramdac testing power on reset = 00 note: see appendix e for further details. ccr7d: control registers for tv and ramdac testing read/write address: 3c5h, index: 7dh power-on default: 00h bit 7 tv detect (tv) 0 = normal operation 1 = use ccr7a, ccr7b, and ccr7c data to check for tv detect bit 6 read only for svhs detect (svhs) bit 5 read only for cvbs detect (cvbs) bit 4 monitor detect (md) 0 = normal operation 1 = use ccr7a, ccr7b, and ccr7c data to check for monitor detect bit 3 external vclk 0 = normal operation 1 = enable external vclk 76543210 scratch register 76543210 tv and ramdac testing power on reset = 00 76543210 tv svhs cvbs md vclk mclk r crt
20 - 30 extended smi io mapped registers silicon motion ? , inc. SM731 confidential databook bit 2 external mclk 0 = normal operation 1 = enable external mclk bit 1 reserved bit 0 crt/panel simul mode control register bit (crt) 0 = select crtrgb data to drive the crtdac crtvsync, crthsync is going through the dpms logic to drive the crtvsync and crthslync output 1 = select fpdata to drive the crtdac fpvsync, fphsync is going through the dpms logic to drive the crtvsync and crthsync output note: see appendix e for further details. ccr94: mck pll numerator adjustment read/write address: 3c5h, index: 94h power-on default: 00h in ?powersaving? mode and 3d is off ccr6a value is redu ced by subtracting ccr94 to control mck pll?s numerator. bit 7:0 mck pll numerator adjustment ccr95: mck2 pll numerator adjustment read/write address: 3c5h, index: 95h power-on default: 00h in ?powersaving? mode and 3d is off ccr63 value is reduced by subtracting ccr95 to control mck2 pll?s numerator. bit 7:0 mck2 pll numerator adjustment ccr96: mck pll numerator adjustment 2 read/write address: 3c5h, index: 96h power-on default: 00h in ?poweridle? mode and 3d is off ccr6a value is reduced by subtracting ccr96 to control mck pll?s numerator. 76543210 mck pll numerator adjustment 76543210 mck2 pll numerator adjustment
extended smi io mapped registers 20 - 31 silicon motion ? , inc. SM731 confidential databook bit 7:0 mck pll numerator adjustment ccr97: mck2 pll numerator adjustment 2 read/write address: 3c5h, index: 97h power-on default: 00h in ?poweridle? mode and 3d is off ccr63 value is redu ced by subtracting ccr97 to control mck2 pll?s numerator. bit 7:0 mck2 pll numerator adjustment ccr98: mck pll numerator adjustment 3 read/write address: 3c5h, index: 98h power-on default: 00h in ?powernormal? mode and 3d is on ccr6a value is reduced by subtracting ccr98 to control mck pll?s numerator. bit 7:0 mck pll numerator adjustment ccr99: mck2 pll numerator adjustment 3 read/write address: 3c5h, index: 99h power-on default: 00h in ?powernormal? mode and 3d is on ccr63 value is redu ced by subtracting ccr99 to control mck2 pll?s numerator. bit 7:0 mck2 pll numerator adjustment ccr9a: mck pll numerator adjustment 4 read/write address: 3c5h, index: 9ah 76543210 mck pll numerator adjustment 76543210 mck2 pll numerator adjustment 76543210 mck pll numerator adjustment 76543210 mck2 pll numerator adjustment
20 - 32 extended smi io mapped registers silicon motion ? , inc. SM731 confidential databook power-on default: 00h in ?powersaving? mode and 3d is on ccr6a value is reduced by subtracting ccr9a to control mck pll?s numerator. bit 7:0 mck pll numerator adjustment ccr9b: mck2 pll numerator adjustment 4 read/write address: 3c5h, index: 9bh power-on default: 00h in ?powersaving? mode and 3d is on ccr63 value is redu ced by subtracting ccr9b to control mck2 pll?s numerator. bit 7:0 mck2 pll numerator adjustment ccr9c: mck pll numerator adjustment 5 read/write address: 3c5h, index: 9ch power-on default: 00h in ?poweridle? mode and 3d is on ccr6a value is reduced by subtracting ccr9c to control mck pll?s numerator. bit 7:0 mck pll numerator adjustment ccr9d: mck2 pll numerator adjustment 5 read/write address: 3c5h, index: 9dh power-on default: 00h in ?poweridle? mode and 3d is on ccr63 value is reduced by subtracting ccr9d to control mck2 pll?s numerator. bit 7:0 mck2 pll numerator adjustment 76543210 mck pll numerator adjustment 76543210 mck2 pll numerator adjustment 76543210 mck pll numerator adjustment 76543210 mck2 pll numerator adjustment
extended smi io mapped registers 20 - 33 silicon motion ? , inc. SM731 confidential databook ccr9e: pll post divider control read/write address: 3c5h, index: 9eh power-on default: 00h the post divider is also controlled by pdr20[5:4]. refer to pdr20[5:4] for the definition. bit 7:6 output divide for m2clk pll 00 = no divide for m2clk pll output 01 = m2clk pll output divide by 4 10 = m2clk pll output divide by 8 11 = m2clk pll output divide by 16 bit 5:4 output divide for mckpll 00 = no divide for mclk pll output 01 = mclk pll output divide by 4 10 = mclk pll output divide by 8 11 = mclk pll output divide by 16 bit 3:2 output divide for vrclk pll 00 = no divide for vrclk pll output 01 = vrclk pll output divide by 4 10 = vrclk pll output divide by 8 11 = vrclk pll output divide by 16 bit 1:0 output divide for vclk pll 00 = no divide for vclk pll output 01 = vclk pll output divide by 4 10 = vclk pll output divide by 8 11 = vsclk pll output divide by 16 general purpose registers gpr70: scratch pad register 1 read/write address: 3c5h, index: 70h power-on default: undefined except for bit [3:0] which are power-on configurable (by reset) this register can be used as general purpose scratch bits. bit 7:4 scratch pad register bits. this register can be used as general purpose bits. 76543210 m2clk pll mclk pll vrclk pll vlk pll 76543210 scratch pad reg bits primary panel id
20 - 34 extended smi io mapped registers silicon motion ? , inc. SM731 confidential databook bit 3:0 primary panel id 0000 = 640 x 480 tft 0001 = 800 x 600 tft 0010 = 1024 x 768 tft 0011 = 1280 x 1024 tft 0100 = 1600 x 1200 tft gpr71: scratch pad register 2 read/write address: 3c5h, index: 71h power-on default: undefined this register can be used as general purpose scratch bits. bit 7:0 scratch pad 2 register. this register can be used as general purpose scratch bits. gpr72: user defined register 1 for ddc2/ i2c read/write address: 3c5h, index: 72h power-on default: 00h this register is used for user defined registers: usr1/sda and usr0/scl. the sda and scl can be used for vesa ddc2 / i2c serial communication port. bit 7:6 reserved bit 5 enable usr1/sda port (eusr1) 0 = disable use of bit 1 of this register 1 = enable use of bit 1 of this register bit 4 enable usr0/scl port (eusr0) 0 = disable use of bit 0 of this register 1 = enable use of bit 0 of this register bit 3 usr1/sda status (read only). this bit can be used for ddc2/i2c data. (usr1s) 0 = pin usr1/sda is low 1 = pin usr1/sda is tri-stated bit 2 usr0/scl status (read only). this bit can be used for ddc2/i2c clock. (usr0s) 0 = pin usr0/scl is low 76543210 scratch pad 2 register 76543210 reserved eusr1 eusr0 usr1s usr0s usr1w usr0w
extended smi io mapped registers 20 - 35 silicon motion ? , inc. SM731 confidential databook 1 = pin usr0/scl is tri-stated bit 1 usr1/sda write. pin 131 can be used for ddc2/i2c data. when pin usr1/sda is tri-stated, other devices may drive this line. the actual state of the pin usr1/sda is read via bit 3 of this register. (usr1w) 0 = pin usr1/sda is driven low 1 = pin usr1/sda is tri-stated bit 0 usr0/scl write. pin 132 can be used for ddc2/i2c clock. when pin usr0/scl is tri-stated, other devices may drive this line. the actual state of the pin usr0/scl is read via bit 2 of this register. (usr0w)0 = pin usr0/scl is driven low 1 = pin usr0/scl is tri-stated note: see appendix d for further details. gpr73: user defined register 2 read/write address: 3c5h, index: 73h power-on default: 00h this register can be used to control user programmable outputs: usr2 and usr3 pins. bit 7:6 reserved bit 5 enable usr3 port (usr3p) 0 = disable use of bit 1 of this register 1 = enable use of bit 1 of this register bit 4 enable usr2 port (usr2p) 0 = disable use of bit 0 of this register 1 = enable use of bit 0 of this register bit 3 user3 status (read only) (user3) 0 = pin usr3 is low 1 = pin usr3 is tri-stated bit 2 user2 status (read only) (user2) 0 = pin usr2 is low 1 = pin usr2 is tri-stated bit 1 usr3 write. when pin usr3 is tri-stated, other devices may drive this line. the actual state of the pin usr3 is read via bit 3 of this register. (usr3w) 0 = pin usr3 is driven low 1 = pin usr3 is tri-stated 76543210 reserved usr3p usr2p user3 user2 usr3w usr2w
20 - 36 extended smi io mapped registers silicon motion ? , inc. SM731 confidential databook bit 0 usr2 write. when pin usr2 is tri-stated, other devices may drive this line. the actual state of the pin usr2 is read via bit 2 of this register. (usr2w) 0 = pin usr2 is driven low 1 = pin usr2 is tri-stated gpr74: scratch pad register 3 read/write address: 3c5h, index: 74h power-on default: undefined this register can be used as general purpose scratch bits. bit 7:0 scratch pad 3 register. this register can be used as general purpose scratch bits. gpr75: scratch pad register 4 read/write address: 3c5h, index: 75h power-on default: undefined this register can be used as general purpose scratch bits. bit 7:0 scratch pad 4 register. this register can be used as general purpose scratch bits. pop-up icon and hardware cursor registers phr80: pop-up icon and hardware cursor pattern location low read/write address: 3c5h, index: 80h power-on default: undefined this register specifies the low 8 bits of the address for pop-up icon and hardware cursor pattern location, which is a 11- bit register. the high order 3 bits are specified in the phr81 [2:0] register. bit 7:0 pop-up icon and hardware cursor pattern location low. the phr80 and phr81 [2:0] registers allocate 2kb off-screen memory within the maxi mum 4mb of physical memory. the lower 1kb is used to store pop-up icon image. the upper 1kb is used to store hardware cursor image 76543210 scratch pad 3 register 76543210 scratch pad 4 register 76543210 pop-up icon and hardware cursor pattern
extended smi io mapped registers 20 - 37 silicon motion ? , inc. SM731 confidential databook phr81: hardware cursor enable & pi/hwc pattern location high read/write address: 3c5h, index: 81h power-on default: 0xh this register specifies the hardware cursor enable and the high-order 3 bits of the address for pop-up icon and hardware cursor pattern location, which is a 11-bit register. the low order 8 bits are specified in the phr80 register. bit 7 hardware cursor enable (hce) 0 = disable (default) 1 = enable bit 6 reserved (r) bit 5:0 pop-up icon and hardware cursor pattern location high. the phr80 and phr81 [2:0] registers allocate 2kb off-screen memory within the maxi mum 32mb of physical memory. the lower 1kb is used to store pop-up icon image. the upper 1kb is used to store hardware cursor image. pop-up icon registers pop82: pop-up icon control read/write address: 3c5h, index: 82h power-on default: 00h this register specifies the control for pop-up icon. bit 7 pop-up icon enable (puie) 0 = disable 1 = enable bit 6 pop-up icon zoom enable (puize) 0 = normal. (pop-up icon size is 64x64x2) 1 = zoom up the pop-up icon size by 2. (pop-up icon size is 128x128x2) bit 5:0 reserved pop83: reserved read/write address: 3c5h, index: 83h power-on default: undefined 76543210 hce r pop-up icon 76543210 puie puize reserved
20 - 38 extended smi io mapped registers silicon motion ? , inc. SM731 confidential databook this register is reserved. bit 7:0 reserved pop84: pop-up icon color 1 read/write address: 3c5h, index: 84h power-on default: undefined this register specifies the color1 for pop-up icon. bit 7:0 pop-up icon color1. pop85: pop-up icon color 2 read/write address: 3c5h, index: 85h power-on default: undefined this register specifies the color2 for pop-up icon. bit 7:0 pop-up icon color2. pop86: pop-up icon color 3 read/write address: 3c5h, index: 86h power-on default: undefined this register specifies the color3 for pop-up icon. bit 7:0 pop-up icon color3. 76543210 reserved 76543210 pop-up icon color1 76543210 pop-up icon color2 76543210 pop-up icon color3
extended smi io mapped registers 20 - 39 silicon motion ? , inc. SM731 confidential databook pop90: pop-up icon start x - low read/write address: 3c5h, index: 90h power-on default: undefined this register specifies pop-up icon location x start [7:1]. the pop icon can only be moved in x direction by increments of 2 pixels. bit [0] has no effect bit 7:1 pop-up icon x start [7:1] bit 0 has no effect (ne) pop91: pop-up icon start x - high read/write address: 3c5h, index: 91h power-on default: undefined this register specifies pop-up icon location x start [11:8] bit 7:3 reserved bit 2:0 pop-up icon x start [10:8] pop92: pop-up icon start y - low read/write address: 3c5h, index: 92h power-on default: undefined this register specifies pop-up icon location y start [7:0] bit 7:0 pop-up icon y start [7:0] pop93: pop-up icon start y - high read/write address: 3c5h, index: 93h power-on default: undefined 76543210 pop-up icon x start [7:0] ne 76543210 reserved pop-up icon x start 76543210 pop-up icon y start
20 - 40 extended smi io mapped registers silicon motion ? , inc. SM731 confidential databook this register specifies pop-up icon location y start [11:8] bit 7:3 reserved bit 2:0 pop-up icon y start [10:8] hardware cursor registers hcr88: hardware cursor upper left x position - low read/write address: 3c5h, index: 88h power-on default: 00h this register specifies the lower 8-bit upper left x position for hardware cursor. bit 7:0 hardware cursor x position low order 8 bits. the high order 3 bits are in hcr89[2:0]. hcr89: hardware cursor upper left x position- high read/write address: 3c5h, index: 89h power-on default: 00h this register specifies the upper left x position for hardware cursor. bit 7:4 reserved bit 3 hardware cursor upper left x position boundary select (hcul) 0 = hardware cursor is within the screen left side boundary. {hcr89[2:0], hcr88[7:0]} specify the x position of the hardware cursor from the left side boundary. 1 = hardware cursor is partially or totally outside of the left side screen boundary. hcr88 [4:0] specify how many pixels of the hardware cursor are outside the left side screen boundary. bit 2:0 hardware cursor x position high-order 3 bits. the low order 8 bits are specified in the hcr88 register. (hcxp) 76543210 reserved pop-up icon y start 76543210 hardware cursor x position low order 76543210 reserved hcul hcxp
extended smi io mapped registers 20 - 41 silicon motion ? , inc. SM731 confidential databook hcr8a: hardware cursor upper left y position - low read/write address: 3c5h, index: 8ah power-on default: 00h this register specifies the upper left y position for hardware cursor. bit 7:0 hardware cursor y position low order 8 bits. the high order 3 bits are in hcr8b [2:0]. hcr8b: hardware cursor upper left y position - high read/write address: 3c5h, index: 8bh power-on default: 00h this register specifies the upper left y position for hardware cursor. bit 7:4 reserved bit 3 hardware cursor upper left y boundary select (hcul) 0 = hardware cursor is within the screen top side boundary. {hcr8b[2:0], hcr8a[7:0]} specify the y position of the hardware cursor from the top side boundary. 1 = hardware cursor is partially or totally outside of the top side screen boundary. hcr8a [4:0] specify how many pixels of the hardware cursor are outside the top side screen boundary. bit 2:0 hardware cursor y position high-order 3 bits. the lo w order 8 bits are specified in the hcr8a register. (hcyp) hcr8c: hardware cursor foreground color read/write address: 3c5h, index: 8ch power-on default: 00h this register specifies the foreground color for hardware curs or. hardware cursor is always in 24-bit color. the 24-bit color is the expansion of 3:3:2 rgb into 8:8:8 rgb color. bit 7:0 hardware cursor foreground color this register defines 3:3:2 8-bit rgb of the hardware cursor foreground color. 76543210 hardware cursor y position low order 76543210 reserved hcul hcyp 76543210 hardware cursor foreground color
20 - 42 extended smi io mapped registers silicon motion ? , inc. SM731 confidential databook hcr8d: hardware cursor background color read/write address: 3c5h, index: 8dh power-on default: 00h this register specifies the background color for hardware curs or. hardware cursor is always in 24-bit color. the 24-bit color is the expansion of 3:3:2 rgb into 8:8:8 rgb color. bit 7:0 hardware cursor background color this register defines 3:3:2 8-bit rgb of the hardware cursor background color. extended crt control registers crt30: crtc overflow and interlace mode enable read/write address: 3?5h, index: 30h power-on default: 00h this register specifies the crtc overflow registers and interlace mode enable. bit 7 interlace mode enable (ime) 0 = disable 1 = enable bit 6:4 bit [18:16] of the crt display starting address. th e lower order 16-bit are located in crtc register index 0ch and 0dh. bit 3 bit 10 of the crt vertical total register. the lower bit [9:0] are defined in crtc register index 07h and 06h. (cvtr) bit 2 bit 10 of the crt vertical display end register. the lower bit [9:0] are defined in crtc register index 12h and 07h. (cvder) bit 1 bit 10 of the crt vertical blank start. the lower bit [9:0] are defined in crtc register index 15 h, 09h, and 07h. (cvbs) bit 0 bit 10 of the crt vertical retrace start. the lower bit [9:0] are defined in crtc register index 10h and 07h. (cvrs) 76543210 hardware cursor background color 76543210 ime crt display cvtr cvder cvbs cvrs
extended smi io mapped registers 20 - 43 silicon motion ? , inc. SM731 confidential databook crt31: interlace retrace read/write address: 3?5h, index: 31h power-on default: 00h this register specifies when vertical retrace begins. this regist er is only valid if interlace mode is enabled (crt30 bit 7 = 1). bit 7:0 specify the number of character units in ho rizontal timing when vertical retrace begins. crt32: tv vertical display enable start read/write address: 3?5h, index: 32h power-on default: 00h this register specifies the vertical display enable start for tv timing. bit 7:0 when crt vertical count = crt32 [7:0], tv vertical display enable become active. crt33: tv vertical display enable end - high read/write address: 3?5h, index: 33h power-on default: 00h this register specifies the vertical display enable end for tv timing. this register is a 11-bit register. the lower 8-bit of this register resides in crt34. bit 7 interlace timing enable for double scan modes (i.e.: mode 13, etc.) (ite) 0 = disable 1 = enable bit 6:5 bit [7:6] of horizontal blank end. bit 5 is located in bit 7 of crtc register, 3?5h, index 5. bit [4:0] is located in crtc register, 3?5h, index 3. (hbe) bit 4:3 bit [9:8] of vertical blank end. bit [7:0] of vertical blank end is located in crtc register, 3?5h, index 16. (vbe) 76543210 specifiy # character units in horizontal timing 76543210 tv vertical display enable 76543210 ite hbe vbe crt vertical count
20 - 44 extended smi io mapped registers silicon motion ? , inc. SM731 confidential databook bit 2:0 when crt vertical count = {crt33 [2:0],crt34 [7:0]} , tv vertical display enable becomes inactive. crt34: tv vertical display enable end - low read/write address: 3?5h, index: 34h power-on default: 00h this register specifies the vertical display enable end for tv timing. bit 7:0 when crt vertical count = {crt33 [2:0],crt34 [7:0 ]} tv vertical display enable becomes inactive. crt35: vertical screen expansion dda control constant - low read/write address: 3?5h, index: 35h power-on default: 00h this register specifies bit [7:0] the dda control constant (ddacc) which is used for vertical screen expansion in vga modes. bit [9:8] of the ddacc is located in crt36. to enable vertical screen expansion in vga graphics modes, one needs to program the dda control constant (ddacc) equal to: to enable vertical expansion in vga text mode, one must program ddacc [2:0] = # of times the last character row should be repeated. bit 7:0 this register defines the lower 8 bits of the vertical screen expansion dda control constant. the upper 2 bits of the ddacc register is located in crt36. for vga text modes, only the lower [2:0] are valid. crt36: vertical screen expansion dda control constant - high read/write address: 3?5h, index: 36h power-on default: 00h this register the vertical screen expansion dda control constant lower 8 bits. 76543210 crt vertical count ddacc = 1024 * actual vertical size expanded vertical size 76543210 vertical screen expansion 76543210 reserved vse
extended smi io mapped registers 20 - 45 silicon motion ? , inc. SM731 confidential databook bit 7:2 reserved bit 1:0 this register defines bit [9:8] of the vertical screen expansion dda control constant. the lower 8-bit are located in crt35. (vse) crt37: hardware/vga test selection/display control read/write address: 3?5h, index: 37h power-on default: 00h bit 7:5 vga test bus selection. these bits select groups of vga signals to test the bus. this is for testing purposes only bit 4 this is used for vga testing only. should default to 0. (vga) 0 = in non vga mode, the display enable and blank signal is 1 character clock (plus 3 pixel clocks) earlier compared with vga mode. 1 = in non vga mode, the display enable and blank signal matches with vga mode timing bit 3 horizontal and vertical display enable (hvde) 0 = normal 1 = lock horizontal and vertical display enable shadow registers bit 2:0 display control 000 = crt display only 001 = lcd display is on. crt shadow registers are locked 010 = crt display only 011 = crt & lcd display. crt shadow registers are locked 100 = tv display 101 = tv & lcd display 110 = in legal setting 111 = in legal setting crt38: extra horizontal timing control read/write address: 3?5h, index: 38h power-on default: 00h bit 7 lock shadow (ls) 0 = normal (default) 1 = lock all shadow registers including crt33 bit [6:3] 76543210 vga test bus vga hvde display control 76543210 ls reserved vb hs hb ht
20 - 46 extended smi io mapped registers silicon motion ? , inc. SM731 confidential databook bit 6:4 reserved bit 3 vertical blank end bit [10] (vb) bit 2 horizontal sync start bit [8] (hs) bit 1 horizontal blank end bit [8] (hb) bit 0 horizontal total bit [8] (ht) crt39: scratch register read/write address: 3?5h, index: 39h power-on default: 00h bit 7:0 scratch register crt3a: tv total timing control for the internal tv encoder read/write address: 3?5h, index: 3ah power-on default: 00h bit 7:6 reserved bit 5:3 00 = normal 01 = hsync delayed by one pixel clock 02 = hsync delayed by two pixel clock 03 = hsync delayed by three pixel clock 04 = hsync delayed by four pixel clock 05 = hsync delayed by five pixel clock bit 2:0 07 = one character cloc k contains 7 dot clocks 06 = one character cloc k contains 6 dot clocks 05 = one character cloc k contains 5 dot clocks 04 = one character cloc k contains 4 dot clocks 03 = one character cloc k contains 3 dot clocks 02 = one character cloc k contains 2 dot clocks 01 = one character cloc k contains 1 dot clocks 00 = one character cloc k contains 0 dot clocks for example, to program 910 pixel horizontal total for 4fc ntsc tv mode: 76543210 scratch register 76543210 reserved hsync dot clocks
extended smi io mapped registers 20 - 47 silicon motion ? , inc. SM731 confidential databook program crt horizontal total regist er to be 109 character clock program 3?4 index 3a bit [2:0] = 06 the actual total number of characters per horizontal line is 109 + 5 = 114 the horizontal total in pixel clock is: 113 x 8 + 6 = 910 crt3b: miscellaneous lock register i read/write address: 3?5h, index: 3bh power-on default: 00h bit 7:0 reserved for vga hardware testing crt3c: miscellaneous lock register ii read/write address: 3?5h, index: 3ch power-on default: 00h bit 7:6 reserved vga hardware debug test bus selection bit 5 blanking signal selection (bss) 0 = the blanking signal sent to ramdac is reversed active display. outside of active display the blanking is active (black color). the border color register has no effect. 1 = the blank signal sent to ramdac is the normal blank signal from crt. when both the blank and dispen are inactive the border color is displayed. bit 4 vga line compare register (crt09 [6] and crt07 [4]) force (vgalc) 0 = normal (default) 1 = enable. force line compare [9:8] to be high. th e original line compare control bits [9:8] have no effect. this register is used for japanese dos hardware scrolling compatibility purpose. bit 3:2 for testing blinking logic text mode bit [2] = 1 enable test mode bit [3] = 1 for blank to act bit 1:0 select lcd character/cursor blink rate in text modes 00 = character/cursor blink every 16 frames 01 = character/cursor blink every 32 frames 1x = character/cursor blink every 64 frames 76543210 reserved for vga hardware testing 76543210 reserved bss vgalc blinking logic blink rate
20 - 48 extended smi io mapped registers silicon motion ? , inc. SM731 confidential databook crt3d scratch register bits read/write address: 3?5h, index: 3dh power-on default: bit 7:0 scratch register bit crt3e: scratch register bits read/write address: 3?4h, index: 3eh power-on default: 00h bit 7:0 scratch register bits crt3f: scratch register bits read/write address: 3?4h, index: 3fh power-on default: 00h bit 7:0 scratch register bits crt9e: expansion/centering control register 2 read/write address: 3?4h, index: 9eh power-on default: 00h bit 7 font expansion control bit (fe) this bit is effective if the following is true: crt9e_ [4] = 0 and the text mode plus the vertical expansion is on and crt09_[4:0] < h0f 0 = the font vertical expansion wi ll repeat the last character row 1 = the font vertical expansion will insert lines (with screen background color) between the last scan line of the current character row and the first scan of the next character row. 76543210 scratch register bits 76543210 scratch register bits 76543210 scratch register bits 76543210 fe hscrt hsrw ve vc vee vce hce
extended smi io mapped registers 20 - 49 silicon motion ? , inc. SM731 confidential databook bit 6 horizontal shadow register selection for crt timing control (hscrt) 0 = there are two sets of horizontal shadow register s (primary and secondary). the selection switch is at the beginning of the vsync. if cr9f_[0] or cr9f [1] is equal to 1 the second set is selected. if these registers are not equal to 1 then the primary set is selected. 1 = to force the selection of the second set of horizontal shadow register bit 5 horizontal shadow register read/write selection (hsrw) the following register update are effected svr40_[7:0] - horizontal total shadow svr41_[7:0] - horizontal blank start shadow svr42_[4:0] - horizontal blank end shadow svr44_[7] - horizontal blank end bit 5 shadow crt33_[6:5] - horizontal blank end bit 7 & 6 svr43_[7:0] - horizontal sync start shadow svr44_[4:0] - horizontal sync end crt9f_[0] - 10 dots expansion crt9f_[1] - 12 dots expansion these registers have two sets - primary and secondary. bit 5=0: the primary registers are selected for w/r and control crt bit 5=1: the secondary registers are selected for w/r and control crt bit 4 vertical expansion dda value selection (ve) 0 = vertical expansion will select the dda value from the dda look up table (3?4.35&36). this bit has no effect if bit 2 of this register = 0. 1 = vertical expansion will select the dda value from the dda look up table (3?4.90-91b). bit 3 vertical centering offset value selection (vc) 0 = select vertical centering offset value from vertical center offset register (3?4, index a6). this bit has no effect if bit 1 of this register = 0 1 = select vertical centering offset value from a look-up table (look up by vdispend) bit 2 vertical expansion enable selection (vee) 0 = vertical expansion disable 1 = vertical expansion enable bit 1 vertical centering enable selection (vce) 0 = vertical centering disable 1 = vertical centering enable bit 0 horizontal centering enable selection (hce) 0 = horizontal centering disable 1 = horizontal centering enable crt9f: expansion/center control register 1 read/write address: 3?4h, index: 9fh power-on default: 00h
20 - 50 extended smi io mapped registers silicon motion ? , inc. SM731 confidential databook bit 7:4 reserved bit 3 for hardware testing only (ht) 0 = vga mode use non divide by 2 video clock. extended vga mode use divide by 2 video clock 1 = reserved for 16 dot expansion. should set to 0. bit 2 blank pixel 0 = normal 1 = in 10 dots expansion mode, this bit if set to 1 will insert blank pixels between characters in vga text modes. bit 1 12 dot expansion (cc12) 0 = 12 dots expansion disabled 1 = character clock expand to 12 dots regardless of bit 0 of this register bit 0 10 dot expansion (cc10) 0 = 10 dots expansion 1 = character clock expand to 10 dots crt90-9b vertical dda look up table & crta0-a5: vertical centering offset look up table read/write address: 3?4, index a0h-a5h power-on default: 00h field 3: this field compared with vdisp_end (3?4.12 bit_[7:2]) field 2: this field is selected dda value if field 3 compares field 1: this field is selected vertical centering offs et value if field 3 compares. the actual offset value = 3?4.a0_[5:0] x 4 the vertical expansion/centering using look up table is enabled only if the following conditions are true: cr9e_[3:1] = 111; if the compare fails to match with any entry, the value from 3?4.a6 will be used for vertical centering and the 3?4.35&36 will be used for dda. the following register groups behave the same: 3?4.92; 3?4.93; 3?4.a1 3?4.94; 3?4.95; 3?4.a2 76543210 reserved ht 16dot cc12 cc10 3?4.90 3?4.91 3?4.a0 7654321076543210 5 4 3 210 field 3 field 2 field 1
extended smi io mapped registers 20 - 51 silicon motion ? , inc. SM731 confidential databook 3?4.96; 3?4.97; 3?4.a3 3?4.98; 3?4.99; 3?4.a4 3?4.9a; 3?4.9b; 3?4.a5 crta0-a5: vertical centering offset look up table read/write address: 3?4, index a0h-a5h power-on default: 00h field 3: this field compared with vdisp_end (3?4.12 bit_[7:2]) field 2: this field is selected dda value if field 3 compares field 1: this field is selected vertical centering offs et value if field 3 compares. the actual offset value = 3?4.a0_[5:0] x 4 the vertical expansion/centering using look up table is enabled only if the following conditions are true: cr9e_[3:1] = 111; if the compare fails to match with any entry, the value from 3?4.a6 will be used for vertical centering and the 3?4.35&36 will be used for dda. the following register groups behave the same: 3?4.92; 3?4.93; 3?4.a1 3?4.94; 3?4.95; 3?4.a2 3?4.96; 3?4.97; 3?4.a3 3?4.98; 3?4.99; 3?4.a4 3?4.9a; 3?4.9b; 3?4.a5 crta6: vertical centering offset register read/write address: 3?4, index: a6h power-on default: 00h bit 7:6 reserved bit 5:0 specifies how many lines the screen image will shift down. this register will have no effect if 3?4.9e bit_[1]=1 3?4.90 3?4.91 3?4.a0 7654321076543210 5 4 3 210 field 3 field 2 field 1 76543210 reserved line shift down
20 - 52 extended smi io mapped registers silicon motion ? , inc. SM731 confidential databook crta7: horizontal centering offset register read/write address: 3?4h, index: a7h power-on default: 00h bit 7 reserved (r) bit 6:0 specifies how many character units the screen image will shift to the right. this register has no effect if 3?4.9e bit_[0] = 0. 0 = use to specify how many character units the screen image will shift to the right to center position. the horizontal screen centering look up table has no effect. 1 = to enable horizontal shift look up table (crt9e_[0] has to be 1). one of the table entry will be select and the value in the entry specifies how many character units the screen image will shift to the right center position. the selection of the look up is as follows: if crt01_[7:1] = crta8_[6:0] control screen centering. else if crt01_[7:1] = crtaa_[6:0], crtab_[6:0] control screen centering. else if crt01_[7:1] = crtac_[6:0], crtad_[6:0] control screen centering. else cra7_[6:0] will be used as default to control screen centering. crta8-ad: horizontal screen centering look up table read/write address: 3?4, index a8h-adh power-on default: 00h bit 7: reserved bit 6:0 horizontal screen centering look up table shadow vga registers the shadow vga registers are designed to control crt, lcd and tv timing, and maintain vga compatibility. SM731 shadows 12 vga crt registers. when these shadow register s are unlocked, the cpu i/o wr ite operation can write into both standard crt registers and shadow registers through standard vga crtc i/o location. when these shadow registers are locked, the cpu i/o write can only write into the standard crt registers through crtc i/o location. these 12 shadow registers also have specific i/o location wh ich is not controlled by shadow lock/unlock register. 76543210 r character unit shift right 76543210 r horizontal screen centering look up table
extended smi io mapped registers 20 - 53 silicon motion ? , inc. SM731 confidential databook automatic lock/unlock scheme for shadow registers there are two ways to access shadow registers. one is thro ugh standard vga crtc i/o lo cation when crt is the only selected display. these vga crt i/o write operations will write to both standard vga crt registers and shadow registers. the other way to access shadow registers is through their dedicated i/o locations. the shadow registers can only be read through their dedicated i/o locations. when lcd or tv display is selected, the shadow regi sters will be automatically locked. the vga crt i/o write operation will write only to the standard vga crt registers. the shadow registers have to be accessed from their dedicated i/o location. this approach will reduce programming difficulty and maintain vga compatibility. svr40: shadow vga horizontal total read/write address: 3?5h, index: 40h power-on default: 00h this register shadows vga crt horizontal total register. bit 7:0 defines the total character count minus 5 characters per horizontal scan line. this register only depends on the resolution of lcd, not the type of lcd. svr41: shadow vga horizontal blank start read/write address: 3?5h, index: 41h power-on default: 00h this register shadows vga crt horizontal blank start register. bit 7:0 when the horizontal character = svr41 [7:0], shadow vga horizontal blank become active. svr40 - horizontal total svr45 - vertical total svr4a - overflow (bit 7, 6,5, 3, 2, 1,and 0) svr41 - start horizontal blanking svr46 - start vertical blank svr4b - maximum scan line (bit 5 only) svr42 - end horizontal blanking svr47 - end vertical blank svr4c - horizontal display end svr43 - start horizontal retrace svr48 - vertical retrace start svr4d - vertical display end svr44 - end horizontal retrace svr49 - vertical retrace end 76543210 shadow vga horizontal total 76543210 shadow vga horizontal blank
20 - 54 extended smi io mapped registers silicon motion ? , inc. SM731 confidential databook svr42: shadow vga horizontal blank end read/write address: 3?5h, index: 42h power-on default: 00h this register shadows vga crt horizontal blank end register. bit 7 reserved (r) bit 6:5 shadows display enable skew control (sdes) bit 4:0 when the horizontal character = {svr44 [7],svr42 [4:0]}, shadow vga horizontal blank become inactive. svr43: shadow vga horizontal retrace start read/write address: 3?5h, index: 43h power-on default: 00h this register shadows vga crt horizontal retrace start register. bit 7:0 when the horizontal character = svr43 [7:0], shadow vga horizontal retrace become active. svr44: shadow vga horizontal retrace end read/write address: 3?5h, index: 44h power-on default: 00h this register shadows vga crt horizontal retrace end register. bit 7 when the horizontal character = {svr44 [7],svr41 [4:0]}, shadow vga horizontal blank become inactive. (svhb) bit 6:5 shadows horizontal retrace delay (shrd) bit 4:0 when the horizontal character = svr44 [4:0], shadow vga horizontal retrace become inactive. 76543210 r sdes shadow vga horizontal blank inactive 76543210 shadow vga horizontal retrace inactive 76543210 svhb shrd shadow vga horizontal retrace inactive
extended smi io mapped registers 20 - 55 silicon motion ? , inc. SM731 confidential databook svr45: shadow vga vertical total read/write address: 3?5h, index: 45h power-on default: 00h this register shadows vga crt vertical total register. bit 7:0 shadows the least significant 8 bits of 11 bits count of raster scan lines for display frame. svr46: shadow vga vertical blank start read/write address: 3?5h, index: 46h power-on default: 00h this register shadows vga crt vertical blank start register. bit 7:0 shadows the least significant 8-bit of the 11-bit vga crt vertical blank start register. svr47: shadow vga vertical blank end read/write address: 3?5h, index: 47h power-on default: 00h this register shadows vga crt vertical blank end register. bit 7:0 shadows the least significant 8-bit vga crt vertical blank end register. svr48: shadow vga vertical retrace start read/write address: 3?5h, index: 48h power-on default: 00h this register shadows vga crt vertical retrace start register. 76543210 shadow vga vertical total 76543210 shadow vga vertical blank start 76543210 shadow vga vertical blank end
20 - 56 extended smi io mapped registers silicon motion ? , inc. SM731 confidential databook bit 7:0 shadows the least significant 8-bit of th e 11-bit vertical retrace start register. svr49: shadow vga vertical retrace end read/write address: 3?5h, index: 49h power-on default: 00h this register shadows vga crt vertical retrace end register. bit 7:4 reserved bit 3:0 shadows bit [3:0] of vga crt vertical retrace end register. svr4a: shadow vga vertical overflow read/write address: 3?5h, index: 4ah power-on default: 00h this register shadows vga crt vertical overflow register. bit 7 shadows vertical retrace start bit 9 (svrs9) bit 6 shadow vertical display enable bit 9 (3?5h, index 7 [6]). when crt37[3] = 1, can only access this bit through 3?5h, index 4ah. (svde9) bit 5 shadows vertical total bit 9 (svtb9) bit 4 reserved (r) bit 3 shadows vertical blank start bit 8 (svbs) bit 2 shadows vertical retrace start bit 8 (svrs8) bit 1 shadow vertical display enable bit 8 (3?5h, index 7 [1]). when crt37[3] = 1, can only access this bit through 3?5h, index 4ah. (svde8) 76543210 shadow vga vertical retrace start 7654321 0 reserved shadow vga/crt vertical retrace 76543210 svrs9 svde9 svtb9 r svbs svrs8 svde8 svtb8
extended smi io mapped registers 20 - 57 silicon motion ? , inc. SM731 confidential databook bit 0 shadows vertical total bit 8 (svtb8) svr4b: shadow vga maximum scan line read/write address: 3?5h, index: 4bh power-on default: 00h this register shadows vga crt maximum scan line register. bit 7:6 shadow 3c2 bit_[7:6] for sync polarity (ssp) bit 5 shadows vertical blank start bit 9 (svbs) bit 4:0 reserved svr4c: shadow vga horizontal display end read/write address: 3?5h, index: 4ch power-on default: 00h this register shadows vga crt horizontal display end. bit 7:0 shadows horizontal display end register (3?5h, in dex 01). when crt37[3] = 1, it locks access to this register only through 3?5h, index 4ch. svr4d: shadow vga vertical display end read/write address: 3?5h, index: 4dh power-on default: 00h this register shadows vga crt vertical display end. bit 7:0 shadows vertical display end register [7:0] (3?5h, index 12) when crt37[3] = 1, it locks access to this register only through 3?5h, index 4dh. 76543210 ssp svbs reserved 76543210 shadow horizontal display end 76543210 shadow vertical display end

flat panel processor registers 21 - 1 silicon motion ? , inc. SM731 confidential databook chapter 21: flat panel processor registers table 24: extended smi registers quick reference summary of registers page fpr00: miscellaneous graphics and video control 21 - 4 fpr04: color keys 21 - 6 fpr08: color key masks 21 - 7 fpr0c: data source start address for extended graphics modes 21 - 7 fpr10: data source width and offset for extended graphics modes 21 - 8 fpr14: video window i left and top boundaries 21 - 8 fpr18: video window i right and bottom boundaries 21 - 8 fpr1c: video window i source start address 21 - 9 fpr20: video window i source width and offset 21 - 9 fpr24: video window i stretch factor 21 - 10 fpr28: video window ii left and top boundaries 21 - 10 fpr2c: video window ii right and bottom boundaries 21 - 11 fpr30: video window ii source start address 21 - 11 fpr34: video window ii source width and offset 21 - 12 fpr38: video window ii stretch factor 21 - 12 fpr3c: graphics and video control ii 21 - 13 fpr40: sub picture scale factor 21 - 14 fpr44: sub picture scale factor lsb 21 - 14 fpr48: video window i chroma data source starting address 21 - 15 fpr4c: video window ii chroma data source starting address 21 - 15 fpr50: sub-picture data source starting address 21 - 15 fpr54: fifo priority control 21 - 16 fpr58: fifo empty request level control 21 - 16 fpr5c: yuv to rgb conversion constant 21 - 17 fpr60: current scan line position 21 - 18 fpr64: signature analyzer control and status 21 - 18 fpr68: video window i scale factor lsb 21 - 19 fpr6c: video window ii scale factor lsb 21 - 19
21 - 2 flat panel processor registers silicon motion ? , inc. SM731 confidential databook fpr70: sub picture color look up register 0 21 - 20 fpr74: sub picture color look up register 1 21 - 20 fpr78: sub picture color look up register 2 21 - 21 fpr7c: sub picture color look up register 3 21 - 21 fpr80: sub picture color look up register 4 21 - 21 fpr84: sub picture color look up register 5 21 - 22 fpr88: sub picture color look up register 6 21 - 22 fpr8c: sub picture color look up register 7 21 - 22 fpr90: sub picture color look up register 8 21 - 23 fpr94: sub picture color look up register 9 21 - 23 fpr98: sub picture color look up register a 21 - 23 fpr9c: sub picture color look up register b 21 - 24 fpra0: sub picture color look up register c 21 - 24 fpra4: sub picture color look up register d 21 - 24 fpra8: sub picture color look up register e 21 - 25 fprac: sub picture color look up register f 21 - 25 fprb0: sub picture top/left boundary 21 - 25 fprb4: sub picture bottom/right boundary 21 - 26 fprb8: sub picture source data address offset and line width 21 - 26 fprc0: data source last start address for extended graphics modes 21 - 26 fprc4: data source last start address for video window i 21 - 27 fprc8: data source last start address for video window ii 21 - 27 fprcc: chroma last start address for video window i 21 - 28 fprd0: chroma last start address for video window ii 21 - 28 fprd4: horizontal filter for video window i 21 - 28 fprd8: vertical filter for video window i 21 - 29 fprdc: horizontal filter for video window ii 21 - 29 fpre0: data source last start address for sub picture 21 - 30 fpre4: video window i source odd field start address 21 - 30 fpre8: video window i odd field chroma data source starting address 21 - 30 fprec: data source odd field last start address for video window i 21 - 31 fprf0: odd field chroma last start address for video window i 21 - 31 fpr100: panel interface selection controls 21 - 31 fpr104: wfifo, lcdram, line buffer dda controls 21 - 35 fpr108 : wfifo start address 21 - 37 fpr10c : wfifo off-set address 21 - 37 fpr110 : lcd horizontal display enable horizontal total 21 - 37 summary of registers (continued) page
flat panel processor registers 21 - 3 silicon motion ? , inc. SM731 confidential databook fpr114 : hsync pulse width, vsync pulse width & horizontal sync start 21 - 38 fpr118 : vertical display count and vertical total count 21 - 38 fpr11c: jitter control 21 - 39 fpr120 : panel power down control register 21 - 40 fpr124 : horizontal dda table line 0 21 - 40 fpr128 : horizontal dda table line 1 21 - 41 fpr12c: horizontal dda table line 2 21 - 41 fpr130: horizontal dda table line 3 21 - 42 fpr134 : vertical dda table line 0 21 - 42 fpr138 : vertical dda table line 1 21 - 43 fpr13c : vertical dda table line 2 21 - 43 fpr140 : vertical dda table line 3 21 - 44 fpr144 : vertical dda table line 4 21 - 44 fpr148 : vertical dda table line 5 21 - 44 fpr14c : vertical dda table line 6 21 - 45 fpr150 : vertical dda table line 7 21 - 45 fpr154: vertical dda table line 8 21 - 46 fpr158: hardware cursor x and y position 21 - 46 fpr15c : pop-up icon pattern, background, and foreground color 21 - 46 fpr160 : pop-up icon enable x & y position 21 - 47 fpr164 : pop-up icon color table 21 - 48 summary of registers (continued) page
21 - 4 flat panel processor registers silicon motion ? , inc. SM731 confidential databook video processor control registers SM731 integrates a concurrent flat panel processor. it can support 2 independent video windows using hardware scaling for any size of video windows at any location of the screen display. the flat panel processor control registers can only be accessed through memory-mapped. fpr00: miscellaneous graphics and video control read/write address: 5800h power-on default: 00000000h this register specifies the controls for graphics and video window i/ii. (where x = don't care) bit 31 display off (doff) 0 = display on 1 = display off (except pop up icon) bit 30 reserved (r) (must be 0) bit 29 reserved (r) bit 28 current display field (field) (read only) 0 = current display even field 1 = current display odd field bit 27 reserved (r) bit 26 enable bob display (ebob) 0 = disable 1 = enable bit 25 reserved bit 24 select video window i source start address same as vide o capture buffer start address. this bit is used to automatically display captured data on video window i without programming video window i source start address register (svwi). 0 = normal. video window i source start address is from fpr1c register. 1 = video window i source start address is equal to capture port buffer i source start address (fpr48) or capture port buffer ii source start address (fpr4c). if single buffer is selected for video capture, video window i source start address is equal to capture port buffer i source address. if double buffer is selected for video capture and capture port buffer i is busy, video window i source start address is equal to capture port buffer ii source address. bit 23:21 reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 doff r r field r ebob r cvwi reserved gdt gde gdf 1514131211109876543210 tvws vwiic r vwiit vwiie vwiif vwic vwil vwit vwie vwif
flat panel processor registers 21 - 5 silicon motion ? , inc. SM731 confidential databook bit 20 graphic data in tile format (gdt) 0 = normal format 1 = tile format bit 19 graphic enable (gde) 0 = disable 1 = enable bit 18:16 graphics data format (gdf) 000 = 8-bit index 001 = 15 -bit 5-5-5 rgb 010 = 16-bit 5-6-5 rgb 011 = 32-bit x-8-8-8 rgb 100 = 24-bit 8-8-8 rgb (packed) 101 = reserved 11x = reserved bit 15 top video window select (tvws) 0 = video window i is on top 1 = video window ii is on top bit 14 color key enable for video window ii (ckeii) 0 = disable 1 = enable bit 13 reserved (r) bit 12 video window ii data in tile format (vwiit) 0 = normal format 1 = tile format bit 11 video window ii enable (vwiie) 0 = disable 1 = enable bit 10:8 video window ii format (vwfii) 000 = 8-bit index 001 = 15-bit 5-5-5 rgb 010 = 16-bit 5-6-5 rgb 011 = 32-bit x-8-8-8 rgb 100 = 24-bit 8-8-8 rgb (packed) 101 = 8-bit 3-3-2 rgb 110 = yuv 4:2:2 111 = yuv 4:2:0 (uv interleave) bit 7 color key enable for video window i (ckei) 0 = disable 1 = enable
21 - 6 flat panel processor registers silicon motion ? , inc. SM731 confidential databook bit 6:5 video window i line of filtering (vwil) 00 = 1 line 01 = 2 line 1x = 4 line (data format cannot be yuv 4:2:0 and bit 29 must set to 1) bit 4 video window i data in tile format (vwit) 0 = normal format 1 = tile format bit 3 video window i enable (vwie) 0 = disable 1 = enable bit 2:0 video window i format (vwif) 000 = 8-bit index 001 = 15-bit 5-5-5 rgb 010 = 16-bit 5-6-5 rgb 011 = 32-bit x-8-8-8 rgb 100 = 24-bit 8-8-8 rgb (packed) 101 = 8-bit 3-3-2 rgb 110 = yuv 4:2:2 111 = yuv 4:2:0 (uv interleave) fpr04: color keys read/write address: 5804h power-on default: undefined this register specifies color keys for the two video windows 8-bit color mode 16-bit color mode 8-bit color mode 16-bit color mode 1 bit 31:24 reserved video window ii color key [15:8] bit 23:16 video window ii color key index video window ii color key [7:0] 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved video window ii color key index 151413121110987654 3210 reserved video window i color key index 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 video window ii color key [15:8] video window ii color key [7:0] 151413121110987654 3210 video window i color key [15:8] video window i color key [7:0]
flat panel processor registers 21 - 7 silicon motion ? , inc. SM731 confidential databook bit 15:8 reserved video window i color key [15:8] bit 7:0 video window i color key index video window i color key [7:0] note 1 : for 24-bit or 32-bit color mode, software will need to repack the color key data into rgb - 5:6:5 (16-bit) format. fpr08: color key masks read/write address: 5808h power-on default: undefined this register specifies color key masks for the two video window. bit 31:16 video window ii color key mask 0 = disable color mask 1 = enable color mask bit 15:0 video window i color key mask 0 = disable color mask 1 = enable color mask fpr0c: data source start address for extended graphics modes read/write address: 580ch power-on default: undefined this register specifies data source start address for extended graphics modes bit 31 graphic data status bit (gdsb) bit 30:22 reserved bit 21:0 graphics data source starting address, in 64-bit segment (gdssa) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 video window ii color key mask 151413121110987654 3210 video window i color key mask 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 gdsb reserved gdssa 151413121110987654 3210 gdssa
21 - 8 flat panel processor registers silicon motion ? , inc. SM731 confidential databook fpr10: data source width and offset for extended graphics modes read/write address: 5810h power-on default: undefined this register specifies data source data line widt h and offset address for extended graphics modes. bit 31:26 reserved bit 25:16 graphics data source data line width, in 64-bit segment bit 15:10 reserved bit 9:0 graphics data start address offset, in 64-bit segment fpr14: video window i left and top boundaries read/write address: 5814h power-on default: undefined this register specifies left and top boundary for video window i. bit 31:27 reserved bit 26:16 video window i, top boundary bit 15:11 reserved bit 10:0 video window i, left boundary fpr18: video window i right and bottom boundaries read/write address: 5818h power-on default: undefined this register specifies right and bottom boundary for video window i. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved graphics data source data line 151413121110987654 3210 reserved graphics data start address offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved video window i top boundary 151413121110987654 3210 reserved video window i left boundary
flat panel processor registers 21 - 9 silicon motion ? , inc. SM731 confidential databook bit 31:27 reserved bit 26:16 video window i, bottom boundary bit 15:11 reserved bit 10:0 video window i, right boundary fpr1c: video window i source start address read/write address: 581ch power-on default: undefined this register specifies video start address for video window i. bit 31 video window i status bit (vwis) bit 30:22 reserved bit 21:0 video window i source start address for, in 64-bit segment. (vwiss) fpr20: video window i source width and offset read/write address: 5820h power-on default: undefined this register specifies video source data line width and offset address for video window i. bit 31:26 reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved video window i bottom boundary 151413121110987654 3210 reserved video window i right boundary 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 vwis reserved vwiss 151413121110987654 3210 vwiss 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved video window i source data line 151413121110987654 3210 reserved video window i source address
21 - 10 flat panel processor registers silicon motion ? , inc. SM731 confidential databook bit 25:16 video window i source data line width, in 64-bit segment bit 15:10 reserved bit 9:0 video window i source address offset, in 64-bit segment fpr24: video window i stretch factor read/write address: 5824h power-on default: 00000000h this register specifies video horizontal and vertical stretch factor for video window i. for optimal display quality, we recommend destination to source ratio to be maximum of 4:1. the two high bytes of this register can be used to enable the ?bob? function. bit 31:24 video window ii initial odd field vertical scale factor bit 23:16 video window ii initial even field vertical scale factor fpr28: video window ii left and top boundaries read/write address: 5828h power-on default: undefined this register specifies left and top boundary for video window ii. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 video window ii inital odd field v ideo window ii initial even field 151413121110987654 3210 video window i horizontal stretch video window i vertical stretch bit 15:8 video window 1 horizontal stretch factor (w1hsf) w1hsf = source destination * 256 note: when stretch factor is set to 0, it becomes a 1-to-1 stretch bit 7:0 video window 1 vertical stretch factor (w1vsf) note: when stretch factor is set to 0, it becomes a 1-to-1 stretch w1vsf = source destinatio n * 256 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved video window ii top boundary 151413121110987654 3210 reserved video window ii left boundary
flat panel processor registers 21 - 11 silicon motion ? , inc. SM731 confidential databook bit 31:27 reserved bit 26:16 video window ii, top boundary bit 15:11 reserved bit 10:0 video window ii, left boundary fpr2c: video window ii right and bottom boundaries read/write address: 582ch power-on default: undefined this register specifies right and bottom boundary for video window ii. bit 31:27 reserved bit 26:16 video window ii, bottom boundary bit 15:11 reserved bit 10:0 video window ii, right boundary fpr30: video window ii source start address read/write address: 5830h power-on default: undefined this register specifies video start address for video window ii. bit 31 video window ii status bits (vwiis) bit 30:22 reserved bit 21:0 video window ii data source starting address (vwiids) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved video window ii bottom boundary 151413121110987654 3210 reserved video window ii right boundary 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 vwiis reserved vwiids 151413121110987654 3210 vwiids
21 - 12 flat panel processor registers silicon motion ? , inc. SM731 confidential databook fpr34: video window ii source width and offset read/write address: 5834h power-on default: undefined this register specifies video source data line width and offset address for video window ii. bit 31:26 reserved bit 25:16 video window ii source data line width, in 64-bit segment bit 15:10 reserved bit 9:0 video window ii source address offset, in 64-bit segment fpr38: video window ii stretch factor read/write address: 5838h/3?5h, index f8, f9, fa, fb power-on default: 00000000h this register specifies video horizontal and vertical stretch factor for video window ii. for optimal display quality, we recommend destination to source ratio to be maximum of 4:1. bit 31:24 video window ii initial odd field vertical scale factor bit 23:16 video window ii initial even field vertical scale factor 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved video window ii source data line 151413121110987654 3210 reserved video window ii source address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 video window ii inital odd field v ideo window ii initial even field 151413121110987654 3210 video window ii horizontal stretch video window ii vertical stretch bit 15:8 video window ii horizontal stretch factor (w2hsf) w2hsf = source destination * 256 note: when stretch factor is set to 0, it becomes a 1-to-1 stretch bit 7:0 video window ii vertical stretch factor (w2vsf) note: when stretch factor is set to 0, it becomes a 1-to-1 stretch w2vsf = source destinatio n * 256
flat panel processor registers 21 - 13 silicon motion ? , inc. SM731 confidential databook fpr3c: graphics and video control ii read/write: address: 583ch power-on default: 00000000h bit 31:24 sub picture horizontal filter 1 (shf1) bit 23:16 sub picture horizontal filter 0 (shf0) bit 15:13 reserved bit 12 color key control sub-picture (ckcs) 0 = disable 1 = enable* * only 8-bit and 16-bit sub-picture data format supported bit 11 sub-picture bi-linear enable (sbe) 0 = disable 1 = enable bit 10:9 sub-picture data format (sf) 00 = 8-bit alpha blending format (alpha_[3:0], color_[3:0]) 01 = 16-bit alpha blending format (alpha_[7:0], color_[7:0]) 1x = 32-bit alpha blending format (alpha_[7:0], color_[23:0]) bit 8 sub-picture enable (se) 0 = disable 1 = enable bit 7 video window ii uv swap enable (evwiiuvs) 0 = disable 1 = enable bit 6:5 reserved bit 4 video window ii horizontal bi-linear enable (evwiihb) 0 = disable 1 = enable bit 3 video window i uv swap enable (evwiuvs) 0 = disable 1 = enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 shf1 shf0 151413121110987654 3 2 1 0 reserved ckcs sbe sf se evwii uvs reserved evwii hb evwi uvs r evwi vb evwi hb
21 - 14 flat panel processor registers silicon motion ? , inc. SM731 confidential databook bit 2 reserved bit 1 video window i vertical bi-linear enable (evwivb) 0 = disable 1 = enable bit 0 video window i horizontal bi-linear enable (evwihb) 0 = disable 1 = enable fpr40: sub picture scale factor read/write address: 5840h power-on default: 00000000h bit 31:24 sub picture initial odd field vertical scale factor bit 23:16 sub picture initial even field vertical scale factor fpr44: sub picture scale factor lsb read/write address: 5844h power-on default: 00000000h bit 31:24 sub picture initial odd field vertical scale factor lsb bit 23:16 sub picture initial even field vertical scale factor lsb 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 sub picture initial odd field vertical sub picture inital even field vertical 151413121110987654 3210 sub picture horizontal scale fact or sub picture vertical scale factor bit 15:8 sub picture horizontal scale factor ghsf = source destination * 256 bit 7:0 sub picture vertical scale factor gvsf = source destination * 256 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 sub picture initial odd field vertical lsb s ub picture inital even field vertical lsb 151413121110987654 3210 sub picture horizontal scale factor ls b sub picture vertical scale factor lsb
flat panel processor registers 21 - 15 silicon motion ? , inc. SM731 confidential databook fpr48: video window i chroma data source starting address read/write address: 5848h power-on default: undefined bit 31:22 reserved bit 21:0 video window i chroma data source starting address fpr4c: video window ii chroma data source starting address read/write address: 584ch power-on default: undefined bit 31:22 reserved bit 21:0 video window ii chroma data source starting address fpr50: sub-picture data source starting address read/write address: 5850h power-on default: undefined bit 15:8 sub picture horizontal scale factor lsb ghsf = source destination * 65536 bit 7:0 sub picture vertical scale factor lsb gvsf = source destination * 65535 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved video window i chroma data source 151413121110987654 3210 video window i chroma data source 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved video window ii chroma data source 151413121110987654 3210 video window ii chroma data source
21 - 16 flat panel processor registers silicon motion ? , inc. SM731 confidential databook bit 31:22 reserved bit 21:0 sub-picture data source starting address fpr54: fifo priority control read/write address: 5854h power-on default: 07216543h this register specifies fifo priority controls for graphics, flat panel read frame buffer fifo1, video window i, video window ii, flat panel write frame buffer, capture window and flat panel read frame bu ffer fifo2. graphics fifo has the highest priority and flat panel read fifo2 has the lowest priority as default. bit 31:0 reserved (must be 0) fpr58: fifo empty request level control read/write address: 5858h power-on default: 00004444h this register specifies fifo empty request level for graphics fifo, video window i, and video window ii. at the specified empty fifo level, fifo request will be generated. default fifo empty levels are all 6 or more empty. for lcd read fifo1/fifo2 and lcd write fifo request leve l controls, they are located in fpr4a register. bit 31:15 reserved bit 14:12 sub picture fifo empty request level select (s fifo) 00x = 2 or more empty 010 = 2 or more empty 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub-picture data source 151413121110987654 3210 sub-picture data source 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 151413121110987654 3210 reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 151413121110987654 3210 r s fifo r vwii fifo r vwi fifo r gfifo
flat panel processor registers 21 - 17 silicon motion ? , inc. SM731 confidential databook 011 = 3 or more empty 100 = 4 or more empty (default) 101 = 5 or more empty 11x = 6 or more empty bit 7 reserved (r) bit 10:8 video window ii fifo empty request level select (vwii fifo) 000 = 2 or more empty 001 = 4 or more empty 010 = 5 or more empty 011 = 6 or more empty 100 = 7 or more empty (default) 101 = 8 or more empty 110 = 10 or more empty 111 = 12 or more empty bit 7 reserved (r) bit 6:4 video window i fifo empty request level select (vwi fifo) 000 = 2 or more empty 001 = 4 or more empty 010 = 5 or more empty 011 = 6 or more empty 100 = 7 or more empty (default) 101 = 8 or more empty 110 = 10 or more empty 111 = 12 or more empty bit 3 reserved (r) bit 2:0 graphics fifo empty request level select (gfifo) 000 = 2 or more empty 001 = 4 or more empty 010 = 5 or more empty 011 = 6 or more empty 100 = 7 or more empty (default) 101 = 8 or more empty 110 = 10 or more empty 111 = 12 or more empty fpr5c: yuv to rgb conversion constant read/write address: 585ch power-on default: edededh this register specifies the yuv to rgb conversion constant.
21 - 18 flat panel processor registers silicon motion ? , inc. SM731 confidential databook bit 31:24 luma y adjustment bit 23:16 red conversion constant bit 15:8 green conversion constant bit 7:0 blue conversion constant fpr60: current scan line position read only address: 5860h power-on default: undefined this register specifies the current scan line position. bit 31:11 reserved bit 10:0 current scan line. this register retu rns the number for current scan line. fpr64: signature analyzer control and status read/write address: 5864h power-on default: undefined this register specifies controls and status for signature analyzer as well as the analyzer signature. bit 31:16 analyzer signature. these bits are ready only. bit 15:4 reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 luma y adjustment red conversion constant 151413121110987654 3210 green conversion constant blue conversion constant 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 151413121110987654 3210 reserved current scan line 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 analyzer signature 151413121110987654 3210 reserved sae sar sass
flat panel processor registers 21 - 19 silicon motion ? , inc. SM731 confidential databook bit 3 signature analyzer enable/stop. software needs to set this bit = 1 as a "enable" control bit in order to enable signature analyzer. once the analysis is completed, the hardware will reset this bit = 0 as a "stop" status bit. (sae) 0 = stop (analysis is completed) 1 = enable (analysis is in progress) bit 2 signature analyzer reset/normal. software needs to set this bit = 1 as a (sar) "reset" control bit to reset signature shift register to "0" before turning on signature analyzer. in the next vertical sync pulse after bit 3 and bit 2 have been set to "11", bit 2 will be automatically reset to "0" as a "normal" status bit. 0 = normal (disable reset to signature analyzer) 1 = reset (enable reset to signature analyzer) bit 1:0 signature analyzer source select. these bits select s the input source for the signature analyzer. (sass) 00 = source is red output from multimedia ramdac 01 = source is green output from multimedia ramdac 1x = source is blue output from multimedia ramdac fpr68: video window i scale factor lsb read/write address: 5868h power-on default: 00000000h bit 31:24 video window i initial odd field vertical scale factor lsb bit 23:16 video window i initial even field vertical scale factor lsb fpr6c: video window ii scale factor lsb read/write address: 586ch power-on default: 00000000h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 vwi initial odd field vertical lsb vwi inital even field vertical lsb 151413121110987654 3210 vwi horizontal scale factor lsb vwi vertical scale factor lsb bit 15:8 video window i horizontal scale factor lsb ghsf = source destination * 65536 bit 7:0 video window i vertical scale factor lsb gvsf = source destination * 65535
21 - 20 flat panel processor registers silicon motion ? , inc. SM731 confidential databook bit 31:24 video window ii initial odd fiel d vertical scale factor lsb bit 23:16 video window ii initial even field vertical scale factor lsb fpr70: sub picture color look up register 0 read/write address: 5870h power-on default: undefined bit 31:24 reserved bit 23:0 sub picture color look up register 0 fpr74: sub picture color look up register 1 read/write address: 5874h power-on default: undefined bit 31:24 reserved bit 23:0 sub picture color look up register 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 vwii initial odd field vertical lsb vwii inital even field vertical lsb 151413121110987654 3210 vwii horizontal scale factor lsb vwii vertical scale factor lsb bit 15:8 video window ii horizontal scale factor lsb ghsf = source destination * 65536 bit 7:0 video window ii vertical scale factor lsb gvsf = source destination * 65535 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture color look up 0 151413121110987654 3210 sub picture color look up 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture color look up 1 151413121110987654 3210 sub picture color look up 1
flat panel processor registers 21 - 21 silicon motion ? , inc. SM731 confidential databook fpr78: sub picture color look up register 2 read/write address: 5878h power-on default: undefined bit 31:24 reserved bit 23:0 sub picture color look up register 2 fpr7c: sub picture color look up register 3 read/write address: 587ch power-on default: undefined bit 31:24 reserved bit 23:0 sub picture color look up register 3 fpr80: sub picture color look up register 4 read/write address: 5880h power-on default: undefined bit 31:24 reserved bit 23:0 sub picture color look up register 4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture color look up 2 151413121110987654 3210 sub picture color look up 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture color look up 3 151413121110987654 3210 sub picture color look up 3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture color look up 4 151413121110987654 3210 sub picture color look up 4
21 - 22 flat panel processor registers silicon motion ? , inc. SM731 confidential databook fpr84: sub picture color look up register 5 read/write address: 5884h power-on default: undefined bit 31:24 reserved bit 23:0 sub picture color look up register 5 fpr88: sub picture color look up register 6 read/write address: 5888h power-on default: undefined bit 31:24 reserved bit 23:0 sub picture color look up register 6 fpr8c: sub picture color look up register 7 read/write address: 588ch power-on default: undefined bit 31:24 reserved bit 23:0 sub picture color look up register 7 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture color look up 5 151413121110987654 3210 sub picture color look up 5 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture color look up 6 151413121110987654 3210 sub picture color look up 6 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture color look up 7 151413121110987654 3210 sub picture color look up 7
flat panel processor registers 21 - 23 silicon motion ? , inc. SM731 confidential databook fpr90: sub picture color look up register 8 read/write address: 5890h power-on default: undefined bit 31:24 reserved bit 23:0 sub picture color look up register 8 fpr94: sub picture color look up register 9 read/write address: 5894h power-on default: undefined bit 31:24 reserved bit 23:0 sub picture color look up register 9 fpr98: sub picture color look up register a read/write address: 5898h power-on default: undefined bit 31:24 reserved bit 23:0 sub picture color look up register a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture color look up 8 151413121110987654 3210 sub picture color look up 8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture color look up 9 151413121110987654 3210 sub picture color look up 9 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture color look up a 151413121110987654 3210 sub picture color look up a
21 - 24 flat panel processor registers silicon motion ? , inc. SM731 confidential databook fpr9c: sub picture color look up register b read/write address: 589ch power-on default: undefined bit 31:24 reserved bit 23:0 sub picture color look up register b fpra0: sub picture color look up register c read/write address: 58a0h power-on default: undefined bit 31:24 reserved bit 23:0 sub picture color look up register c fpra4: sub picture color look up register d read/write address: 58a4h power-on default: undefined bit 31:24 reserved bit 23:0 sub picture color look up register d 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture color look up b 151413121110987654 3210 sub picture color look up b 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture color look up c 151413121110987654 3210 sub picture color look up c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture color look up d 151413121110987654 3210 sub picture color look up d
flat panel processor registers 21 - 25 silicon motion ? , inc. SM731 confidential databook fpra8: sub picture color look up register e read/write address: 58a8h power-on default: undefined bit 31:24 reserved bit 23:0 sub picture color look up register e fprac: sub picture color look up register f read/write address: 58ach power-on default: undefined bit 31:24 reserved bit 23:0 sub picture color look up register f fprb0: sub picture top/left boundary read/write 58b0h power-on default: undefined bit 31:27 reserved bit 26:16 sub picture top boundary bit 15:11 reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture color look up e 151413121110987654 3210 sub picture color look up e 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture color look up f 151413121110987654 3210 sub picture color look up f 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture top boundary 151413121110987654 3210 reserved sub picture left boundary
21 - 26 flat panel processor registers silicon motion ? , inc. SM731 confidential databook bit 10:0 sub picture left boundary fprb4: sub picture bottom/right boundary read/write address: 58b4h power-on default: undefined bit 31:27 reserved bit 26:16 sub picture bottom boundary bit 15:11 reserved bit 10:0 sub picture right boundary fprb8: sub picture source data address offset and line width read/write address: 58b8h power-on default: undefined bit 31:26 reserved bit 25:16 sub picture source data line width bit 15:10 reserved bit 9:0 sub picture source data address offset fprc0: data source last start address for extended graphics modes read/write address: 58c0h power-on default: 3fffff this register specifies data source last starting address for extended graphics modes. when the current line starting address equal or greater then the last start address, the current line starting address will remain the same until next vertica l sync. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture bottom boundary 151413121110987654 3210 reserved sub picture right boundary 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture source data line 151413121110987654 3210 reserved sub picture source data address offset
flat panel processor registers 21 - 27 silicon motion ? , inc. SM731 confidential databook bit 31:22 reserved bit 21:0 graphics data source last starting address, in 64-bit segment fprc4: data source last start address for video window i read/write address: 58c4h power-on default: 3fffff this register specifies data source last starting address for video window i. when the current line starting address equal or greater then the last start address, the current line starting address will remain the same until next vertical sync. bit 31:22 reserved bit 21:0 video window i source last starting address, in 64-bit segment fprc8: data source last start address for video window ii read/write address: 58c8h power-on default: 3fffff this register specifies data source last starting address for vi deo window ii. when the current line starting address equal or greater then the last start address, the current line starting address will remain the same until next vertical sync. bit 31:22 reserved bit 21:0 video window ii source last starting address, in 64-bit segment (vwiislsa) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved graphics data source 151413121110987654 3210 graphics data source 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved video window i source 151413121110987654 3210 video window i source 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved video window ii source 151413121110987654 3210 video window ii source
21 - 28 flat panel processor registers silicon motion ? , inc. SM731 confidential databook fprcc: chroma last start address for video window i read/write address: 58cch power-on default: 3fffff this register specifies chroma last starting address for vi deo window i. when the curren t line starting address equal or greater then the last start address, the current line starting address will remain the same until next vertical sync. bit 31:22 reserved bit 21:0 video window i chroma last starting address, in 64-bit segment fprd0: chroma last start address for video window ii read/write address: 58d0h power-on default: 3fffff this register specifies data source last starting address for video window ii. when the current line starting address equal or greater then the last start address, the current line starting address will remain the same until next vertical sync. bit 31:22 reserved bit 21:0 video window ii chroma last starting address, in 64-bit segment fprd4: horizontal filter for video window i read/write: address: 58d4h power-on default: 000000h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved video window i chroma 151413121110987654 3210 video window i chroma 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved video window ii chroma 151413121110987654 3210 video window ii chroma 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved video window i horizontal filter 2 151413121110987654 3 2 1 0 video window i horizontal filter 1 video window i horizontal filter 0
flat panel processor registers 21 - 29 silicon motion ? , inc. SM731 confidential databook bit 31:24 reserved bit 23:16 video window i horizontal filter 2 bit 15:8 video window i horizontal filter 1 bit 7:0 video window i horizontal filter 0 fprd8: vertical filter for video window i read/write: address: 58d8h power-on default: 00000000h bit 31:24 video window i vertical filter 3 bit 23:16 video window i vertical filter 2 bit 15:8 video window i vertical filter 1 bit 7:0 video window i vertical filter 0 fprdc: horizontal filter for video window ii read/write: address: 58dch power-on default: 000000h bit 31:24 reserved bit 23:16 video window ii horizontal filter 2 bit 15:8 video window ii horizontal filter 1 bit 7:0 video window ii horizontal filter 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 video window i vertical filter 3 video window i vertical filter 2 151413121110987654 3 2 1 0 video window i vertical filter 1 video window i vertical filter 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved video window ii horizontal filter 2 151413121110987654 3 2 1 0 video window ii horizontal filter 1 v ideo window ii horizontal filter 0
21 - 30 flat panel processor registers silicon motion ? , inc. SM731 confidential databook fpre0: data source last start address for sub picture read/write address: 58e0h power-on default: 3fffff this register specifies data source last starting address fo r sub picture. when the curren t line starting address equal or greater then the last start address, the current line starting address will remain the same until next vertical sync. bit 31:22 reserved bit 21:0 sub picture source last starting address, in 64-bit segment fpre4: video window i source odd field start address read/write address: 58e4h power-on default: undefined this register specifies video odd field start address for video window i. bit 31:22 reserved bit 21:0 video window i odd field source start address for, in 64-bit segment. fpre8: video window i odd field chroma data source starting address read/write address: 58e8h power-on default: undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture source 151413121110987654 3210 sub picture source 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved video window i odd field 151413121110987654 3210 video window i odd field 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved video window i odd field chroma data 151413121110987654 3 2 1 0 video window i odd field chroma data
flat panel processor registers 21 - 31 silicon motion ? , inc. SM731 confidential databook bit 31:22 reserved bit 21:0 video window i odd field chroma data source starting address fprec: data source odd field last start address for video window i read/write address: 58ech power-on default: 3fffff this register specifies odd field data source last starting a ddress for video window i. when the current line starting address equal or greater then the last start address, the current line starting address will remain the same until next vertical sync. bit 31:22 reserved bit 21:0 video window i odd field source last starting address, in 64-bit segment fprf0: odd field chroma last start address for video window i read/write address: 58f0h power-on default: 3fffff this register specifies odd field chroma last starting addres s for video window i. when th e current line st arting address equal or greater then the last start address, the current line starting address will remain the same until next vertical sync. bit 31:22 reserved bit 21:0 video window i odd field chroma last starting address, in 64-bit segment flat panel registers fpr100: panel interface selection controls read/write address: 5900h power-on default: 00000000h this registers specifies the different types of flat panel controls. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved video window i odd field 151413121110987654 3210 video window i odd field 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved video window i odd field chroma 151413121110987654 3210 video window i odd field chroma
21 - 32 flat panel processor registers silicon motion ? , inc. SM731 confidential databook bit 31:30 panel hsync adjustment 00: no adjustment 01: move hsync 2 pixel clock ahead 10: move hsync 4 pixel clock ahead 11: move hsync 6 pixel clock ahead bit 29 for panel timing panel only. (phps) 0 = lcd power sequence 1 = bypass hardware power sequence for the fpdata. if select software power sequence, this bit will not function bit 28 for panel timing panel only (pshs) select hardware or software lcd auto-power on/off sequence during display switching in operation or power down modes. this bit can be used to select two different ways to turn on/off lcd panel. for special programming sequence, please refer to the po wer down management chapter of this data book. 0 = select software lcd power sequencing 1 = select hardware lcd power sequencing bit 27:26 for panel timing panel only panel on/off timing select. these two bits are used to control the time period from vbiasen to lcd control signals. these two bits are only vali d when lcd h/w auto-power on/off sequence is selected. 00 = 1 vertical frame 01 = 2 vertical frame 10 = 4 vertical frame 11 = 8 vertical frame bit 25:24 for panel timing panel only panel on/off timing select. these two bits are used to control the time period from fpvddento lcd control signals. these two bits are only vali d when lcd h/w auto-power on/off sequence is selected. 00 = 1 vertical frame 01 = 2 vertical frame 10 = 4 vertical frame 11 = 8 vertical frame bit 23:22 reserved (r) bit 21 for crt timing panel only. (chps) 0 = lcd power sequence 1 = bypass hardware power sequence for the fpdata. if select software power sequence, this bit will not function 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 panel adj phps pshs pp on/off 1 pp on/off 0 reserved chps cshs cp on/off 1 cp on/off 0 1514131211109876543210 l2i l2ds l2en lien lidb l1i msel r lipen lipi fcs r hsp vsp ckp tft
flat panel processor registers 21 - 33 silicon motion ? , inc. SM731 confidential databook bit 20 for crt timing panel only (cshs) select hardware or software lcd auto-power on/off sequence during display switching in operation or power down modes. this bit can be used to select two different ways to turn on/off lcd panel. for special programming sequence, please refer to the po wer down management chapter of this data book. 0 = select software lcd power sequencing 1 = select hardware lcd power sequencing bit 19:18 for crt timing panel only panel on/off timing select. these two bits are used to control the time period from vbiasen to lcd control signals. these two bits are only vali d when lcd h/w auto-power on/off sequence is selected. 00 = 1 vertical frame 01 = 2 vertical frame 10 = 4 vertical frame 11 = 8 vertical frame bit 17:16 for crt timing panel only panel on/off timing select. these two bits are used to control the time period from fpvdden to lcd control signal. these two bits are only va lid when lcd h/w auto-p ower on/off sequence is selected. 00 = 1 vertical frame 01 = 2 vertical frame 10 = 4 vertical frame 11 = 8 vertical frame bit 15 lvds2 panel interface (l2i) 0 = 18 bit panel tx2: de, fp, lp, b5, b4, b3, b2. tx1: b1, b0, g5, g4, g3, g2, g1. tx0: g0, r5, r4, r3, r2, r1, r0. txclk: clock 1 = 24 bit panel refer to bit 9 setting bit 14 lvds2 data select (l2ds) 0 = crt data 1 = panel data bit 13 lvds2 enable bit. (l2en) 0 = disable 1 = enable bit 12 lvds1 enable bit. (lien) 0 = disable 1 = enable bit 11 lvds1 is using for double pixel panel. (lidb) 0 = single pixel 1 = double pixel
21 - 34 flat panel processor registers silicon motion ? , inc. SM731 confidential databook bit 10 lvds1 panel interface (l1i) 0 = 18 bit panel tx2: de, fp, lp, b5, b4, b3, b2 tx1: b1, b0, g5, g4, g3, g2, g1 tx0: g0, r5, r4, r3, r2, r1, r0 txclk: clock 1 = 24 bit panel refer to bit 9 setting bit 9 lvds panel manufacture select (msel) 0 = normal tx3: nc, b7, b6, g7, g6, r7, r6 tx2: de, fp, lp, b5, b4, b3, b2 tx1: b1, b0, g5, g4, g3, g2, g1 tx0: g0, r5, r4, r3, r2, r1, r0 txclk: clock 1 = hitachi tx3: nc, b1, b0, g1, g0, r1, r0 tx2: de, fp, lp, b7, b6, b5, b4 tx1: b3, b2, g7, g6, g5, g4, g3 tx0: g2, r7, r6, r5, r4, r3, r2 txclk: clock bit 8 reserved (r) bit 7 panel 1 without lvds enable bit. (lipen) 1 = enable 0 = disable bit 6 panel 1 interface type select without lvds. (l1pi) 0 = 18-bit 6-bit per r, g, b 1 = 24-bit 8-bit per r, g, b bit 5 panel 1 data select (fcs) 0 = crt data 1 = panel data bit 4 reserved (r) bit 3 panel 1 hsync phase select. (hsp) 0 = normal 1 = inverted hsync bit 2 panel 1 vsync phase select. (vsp) 0 = normal 1 = inverted vsync
flat panel processor registers 21 - 35 silicon motion ? , inc. SM731 confidential databook bit 1 tft fpsclk1 clock phase select. to adjust tft flat panel data timing, user may wish to change the tft fpsclk1 phase by inverting the tft fpsclk1. (ckp) 0 = normal 1 = inverted clock bit 0 color lcd type select. (tft) 0 = color tft 1 = reserved fpr104: wfifo, lcdram, line buffer dda controls read/write address: 5904h power-on default:bit 31-24 are power-on configured by md[15:8]. others are power-on default to zero. this registers specifies the different control signals for wfifo, lcdram, lbuffer and dda modules. bit 31 power-on configured by ma [7] (poc) 0= 1.5v agp pad 1 = 3.3v agp pad bit 30 reserved bit 29:24 reserved for software use with power-on configured by ma [5:0] bit 23:18 reserved bit 17 panel vertical display enable probing (pvd) 1 = on 0 = off bit 16 vertical duplicate pixel enable (vdp) 1 = enable 0 = disable bit 15 horizontal duplicate pixel enable. (hdp) 1 = enable 0 = disable bit 14 reserved (r) bit 13 vertical auto-centering enable (vac) 1 = enable 0 = disable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 poc r reserved reserved pvd vdp 1514131211109876543210 hdp r vac vdda hac hdda lfr lfe lcd1 lcd2 eal watermark pi wififo es
21 - 36 flat panel processor registers silicon motion ? , inc. SM731 confidential databook bit 12 vertical dda enable (vdda) 1 = enable 0 = disable bit 11 horizontal auto-centering enable (hac) 1 = enable 0 = disable bit 10 horizontal dda enable (hdda) 1 = enable 0 = disable bit 9 line fifo ram on/off (lfr) 1 = off 0 = on bit 8 line fifo enable (lfe) 1 = enable 0 = disable bit 7 lcd ram 8/6 bits (lcd1) 0 = 6 bits. 1 = 8 bits. bit 6 lcd ram gamma on (lcd2) 1 = enable 0 = disable bit 5 enable abort line factor (eal) 1 = enable 0 = disable bit 4:3 wfifo water mark 00 = 4 more 01 = 8 more 1x = 12 more bit 2 zero out data except popup icon (pi) 0 = no zero out data 1 = zero out data except popup icon bit 1 wfifo input data 0 = from crt 1 = from panel bit 0 encode select (es) 0 = reserved 1 = rgb 5:6:5
flat panel processor registers 21 - 37 silicon motion ? , inc. SM731 confidential databook fpr108: wfifo start address read/write address: 5908h power-on default: 00000000h wfifo register. bit 31:22 reserved bit 21:0 starting address [21:0] fpr10c: wfifo off-set address read/write address: 590ch power-on default: 00000000h wfifo register bit 31:10 reserved bit 9:0 line offset address [9:0] fpr110: lcd horizontal display enable horizontal total read/write address: 5910h power-on default: 00000000h panel control register bit 31:25 reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved starting address [21:0] 1514131211109876543210 starting address [21:0] 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 reserved line offset address [9:0] 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved horizontal display 1514131211109876543210 reserved horizontal total
21 - 38 flat panel processor registers silicon motion ? , inc. SM731 confidential databook bit 24:16 horizontal display character count [8:0} bit 15:9 reserved bit 8:0 horizontal total character count [8:0] fpr114: hsync pulse width, vsync pulse width & horizontal sync start read/write address: 5914h power-on default: 00000000h panel control register bit 31:29 reserved bit 28:24 hsync pulse width in # of character clocks bit 23:21 reserved bit 20:16 vsync pulse width in # of hsyncs bit 15:9 reserved] bit 8:0 horizontal sync start character count [8:0] fpr118: vertical display count and vertical total count read/write address: 5918h power-on default: 00000000h panel control register bit 31:27 reserved bit 26:16 vertical display count [10:0] 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 resrved hsync pulse reserved vsync pulse 1514131211109876543210 reserved horizontal sync start character count 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved vertical display count 1514131211109876543210 reserved vertical total count
flat panel processor registers 21 - 39 silicon motion ? , inc. SM731 confidential databook bit 15:11 reserved bit 10:0 vertical total count [10:0] fpr11c: jitter control read/write address: 591ch power-on default: 00000000h panel control register bit 31:25 reserved bit 24 jitter control enable (jce) bit 23 reserved bit 22:20 panel 1 fpsclk2 clock delay control 000 = normal 001 = fpsclk2 delays by 1 unit of clock 010 = fpsclk2 delays by 2 unit of clock 011 = fpsclk2 delays by 3 unit of clock 100 = fpsclk2 delays by 4 unit of clock 101 = fpsclk2 delays by 5 unit of clock 110 = fpsclk2 delays by 6 unit of clock 111 = fpsclk2 delays by 7 unit of clock bit 19 reserved bit 18:16 panel 1 fpsclk1 clock delay control 000 = normal 001 = fpsclk1 delays by 1 unit of clock 010 = fpsclk1 delays by 2 unit of clock 011 = fpsclk1 delays by 3 unit of clock 100 = fpsclk1 delays by 4 unit of clock 101 = fpsclk1 delays by 5 unit of clock 110 = fpsclk1 delays by 6 unit of clock 111 = fpsclk1 delays by 7 unit of clock bit 15:11 reserved bit 10:0 vertical sync start [10:0] 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved jce r fpsclk2 delay r fpsclk1 delay 1514131211109876543210 reserved vertical sync start
21 - 40 flat panel processor registers silicon motion ? , inc. SM731 confidential databook fpr120: panel power down control register read/write address: 5920 power-on default: 00030000h panel control register bit 31:26 reserved bit 25 for panel timing panel only (phvs) sync. counter select for power down sequence 0 = vsync 1= hsync bit 24 for crt timing panel only (chvs) sync. counter select for power down sequence 0 = vsync 1= hsync bit 23:18 reserved bit 17 panel timing screen off. (pdf) power on default value for this bit is 1. 0 = screen on. 1 = screen off. bit 16 crt timing screen off. (cdf) power on default value for this bit is 1. 0 = screen on. 1 = screen off. bit 15:8 crt timing panel panel on/off timing se lect. these 8 bits are used to co ntrol the time period from fpen to fpvbiasen. these 8 bits are only valid when lc d h/w auto-power on/off sequence is selected. bit 7:0 panel timing panel on/off timing se lect. these 8 bits are used to co ntrol the time period from fpen to fpvbiasen. these 8 bits are on ly valid when lcd h/w auto-pow er on/off sequence is selected. fpr124: horizontal dda table line 0 read/write address: 5924 power-on default: 00000000h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved phvs chvs reserved pdf cdf 1514131211109876543210 crt timing fpen to fpvbiasen panel timing fpen to fpvbiasen
flat panel processor registers 21 - 41 silicon motion ? , inc. SM731 confidential databook horizontal dda table line 0 (this register is used when the horizontal display value does not compare to fpr128 or fpr130) bit 31 force to use this register as horizontal center value and dda value without compare display value 0 = use compare 1 = force to use this register bit 30:23 reserved bit 22:16 horizontal auto-centering value [6:0] bit 15:0 horizontal dda value [15:0] fpr128: horizontal dda table line 1 read/write address: 5928 power-on default: 00000000h horizontal dda table line 1 bit 31 reserved bit 30:24 hdisp value [6:0] bit 23 reserved bit 22:16 horizontal auto-centering value [6:0] bit 15:0 horizontal dda value [15:0] fpr12c: horizontal dda table line 2 read/write address: 593c power-on default: 00000000h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 fhd reserved horizontal auto centering value 1514131211109876543210 horizontal dda value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r horizontal display value r horizontal auto centering value 1514131211109876543210 horizontal dda value
21 - 42 flat panel processor registers silicon motion ? , inc. SM731 confidential databook horizontal dda table line 2 bit 31 reserved bit 30:24 hdisp value [6:0] bit 23 reserved bit 22:16 horizontal auto-centering value [6:0] bit 15:0 horizontal dda value [15:0] fpr130: horizontal dda table line 3 read/write address: 5930 power-on default: 00000000h horizontal dda table line 3 bit 31 reserved bit 30:24 hdisp value [6:0] bit 23 reserved bit 22:16 horizontal auto-centering value [6:0] bit 15:0 horizontal dda value [15:0] fpr134: vertical dda table line 0 read/write address: 5934 power-on default: 00000000h vertical dda table line 0 (this register is used when th e vertical display value did not compare to fpr138 or fpr154) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r horizontal display value r horizontal auto centering value 1514131211109876543210 horizontal dda value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r horizontal display value r horizontal auto centering value 1514131211109876543210 horizontal dda value
flat panel processor registers 21 - 43 silicon motion ? , inc. SM731 confidential databook bit 31 force to use this register as the vertical cente r value and dda value without compare display value 0 = use compare. 1 = force to use this register. bit 30:25 reserved bit 24:16 vertical auto-centering value [8:0] (# of line) bit 15:0 vertical dda value [15:0] fpr138: vertical dda table line 1 read/write address: 5938 power-on default: 00000000h vertical dda table line 1 bit 31:25 vdisp value [6:0] bit 24:16 vertical auto-centering value [8:0] (# of lines) bit 15:0 vertical dda value [15:0] fpr13c: vertical dda table line 2 read/write address: 593c power-on default: 00000000h vertical dda table line 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 fvd reserved vertical auto centering value 1514131211109876543210 vertical dda value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 vertical display value vertical auto centering value 1514131211109876543210 vertical dda value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 vertical display value vertical auto centering value 1514131211109876543210 vertical dda value
21 - 44 flat panel processor registers silicon motion ? , inc. SM731 confidential databook bit 31:25 vdisp value [6:0] bit 24:16 vertical auto-centering value [8:0] (# of lines) bit 15:0 vertical dda value [15:0] fpr140: vertical dda table line 3 read/write address: 5940 power-on default: 00000000h vertical dda table line 3 bit 31:25 vdisp value [6:0] bit 24:16 vertical auto-centering value [8:0] (# of lines) bit 15:0 vertical dda value [15:0] fpr144: vertical dda table line 4 read/write address: 5944 power-on default: 00000000h vertical dda table line 4 bit 31:25 vdisp value [6:0] bit 24:16 vertical auto-centering value [8:0] (# of lines) bit 15:0 vertical dda value [15:0] fpr148: vertical dda table line 5 read/write address: 5948 power-on default: 00000000h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 vertical display value vertical auto centering value 1514131211109876543210 vertical dda value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 vertical display value vertical auto centering value 1514131211109876543210 vertical dda value
flat panel processor registers 21 - 45 silicon motion ? , inc. SM731 confidential databook vertical dda table line 5 bit 31:25 vdisp value [6:0] bit 24:16 vertical auto-centering value [8:0] (# of lines) bit 15:0 vertical dda value [15:0] fpr14c: vertical dda table line 6 read/write address: 594c power-on default: 00000000h vertical dda table line 6 bit 31:24 vdisp value [6:0] bit 24:16 vertical auto-centering value [8:0] (# of lines) bit 15:0 vertical dda value [15:0] fpr150: vertical dda table line 7 read/write address: 5950 power-on default: 00000000h vertical dda table line 7 bit 31:25 vdisp value [6:0] 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 vertical display value vertical auto centering value 1514131211109876543210 vertical dda value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 vertical display value vertical auto centering value 1514131211109876543210 vertical dda value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 vertical display value vertical auto centering value 1514131211109876543210 vertical dda value
21 - 46 flat panel processor registers silicon motion ? , inc. SM731 confidential databook bit 24:16 vertical auto-centering value [8:0] (# of lines) bit 15:0 vertical dda value [15:0] fpr154: vertical dda table line 8 read/write address: 5954 power-on default: 00000000h vertical dda table line 8 bit 31:25 vdisp value [6:0] bit 24:16 vertical auto-centering value [8:0] (# of lines) bit 15:0 vertical dda value [15:0] fpr158: hardware cursor x and y position read/write address: 5958 power-on default: 00000000h hardware cursor register bit 31:28 reserved bit 27:16 hwc x position high [3:0] and hwc position low [7:0] bit 15:12 reserved bit 11:0 hwc y position high [3:0] and hwc position low [7:0] fpr15c: pop-up icon pattern, background, and foreground color read/write address: 595c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 vertical display value vertical auto centering value 1514131211109876543210 vertical dda value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved hwc x position high and low 1514131211109876543210 reserved hwc y position high and low
flat panel processor registers 21 - 47 silicon motion ? , inc. SM731 confidential databook power-on default: 00000000h hardware cursor fg/bg color register. hwc and pop-up icon pattern. bit 31 hwc enable (hce) 1 = enable 0 = disable bit 30 reserved bit 29:24 pop-up icon/hwc pattern high [5:0] bit 23:16 pop-up icon/hwc pattern low [7:0] bit 15:8 hwc background color [7:0] bit 7:0 hwc foreground color [7:0] fpr160: pop-up icon enable x & y position read/write address: 5960 power-on default: 00000000h pop-up icon control register bit 31:27 reserved bit 26:24 x position high [2:0] bit 23:16 x position low [7:0] bit 15:14 reserved bit 13 pop-up icon enable (pe) 1 = enable 0 = disable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 hce r pop-up icon/hwc pattern high pop-up icon/hwc pattern low 1514131211109876543210 hwc background color hwc foreground color 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved x position high x position low 1514131211109876543210 reserved pe pz r y position high y position low
21 - 48 flat panel processor registers silicon motion ? , inc. SM731 confidential databook bit 12 pop-icon zoom (pz) 0 = normal 1 = zoom up size by 2 bit 11 reserved (r) bit 10:8 y position high [2:0] bit 7:0 y position low [7:0] fpr164: pop-up icon color table read/write address: 5964 power-on default: 00000000h pop-up icon color table bit 31:24 reserved bit 23:16 pop-icon color iii bit 15:8 pop-icon color ii bit 7:0 pop-icon color i 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved pop-up icon color iii 1514131211109876543210 pop-up icon color ii pop-up icon color i
crt processor registers 22 - 1 silicon motion ? , inc. SM731 confidential databook chapter 22: crt processor registers table 25: memory mapped video registers quick reference summary of registers page video processor control registers vpr00: miscellaneous graphics and video control 22 - 3 vpr04: color keys 22 - 5 vpr08: color key masks 22 - 6 vpr0c: data source start address for extended graphics modes 22 - 6 vpr10: data source width and offset for extended graphics modes 22 - 7 vpr14: video window i left and top boundaries 22 - 7 vpr18: video window i right and bottom boundaries 22 - 8 vpr1c: video window i source start address 22 - 8 vpr20: video window i source width and offset 22 - 8 vpr24: video window i stretch factor: 22 - 9 vpr28: video window ii left and top boundaries 22 - 9 vpr2c: video window ii right and bottom boundaries 22 - 10 vpr30: video window ii source start address 22 - 10 vpr34: video window ii source width and offset 22 - 11 vpr38: video window ii stretch factor 22 - 11 vpr3c: graphics and video control ii 22 - 12 vpr40: sub picture scale factor 22 - 13 vpr44: sub picture scale factor lsb 22 - 14 vpr48: video window i chroma data source starting address 22 - 14 vpr4c: video window ii chroma data source starting address 22 - 14 vpr50: sub-picture data source starting address 22 - 15 vpr54: fifo priority control 22 - 15 vpr58: fifo empty request level control 22 - 17 vpr5c: yuv to rgb conversion constant 22 - 18 vpr60: current scan line position 22 - 19 vpr64: signature analyzer control and status 22 - 19 vpr68: video window i scale factor lsb 22 - 20
22 - 2 crt processor registers silicon motion ? , inc. SM731 confidential databook note: some vpr registers can be accessed using memory ma pped register space, or can be accessed using i/o mapped register space. please see register descriptions for detailed information. vpr70: sub picture color look up register 0 22 - 21 vpr74: sub picture color look up register 1 22 - 21 vpr78: sub picture color look up register 2 22 - 22 vpr7c: sub picture color look up register 3 22 - 22 vpr80: sub picture color look up register 4 22 - 22 vpr84: sub picture color look up register 5 22 - 23 vpr88: sub picture color look up register 6 22 - 23 vpr8c: sub picture color look up register 7 22 - 23 vpr90: sub picture color look up register 8 22 - 24 vpr94: sub picture color look up register 9 22 - 24 vpr98: sub picture color look up register a 22 - 24 vpr9c: sub picture color look up register b 22 - 25 vpra0: sub picture color look up register c 22 - 25 vpra4: sub picture color look up register d 22 - 25 vpra8: sub picture color look up register e 22 - 26 vprac: sub picture color look up register f 22 - 26 vprb0: sub picture top/left boundary 22 - 26 vprb4: sub picture bottom/right boundary 22 - 27 vprb8: sub picture source data address offset and line width 22 - 27 vprc0: data source last start address for extended graphics modes 22 - 27 vprc4: data source last start address for video window i 22 - 28 vprc8: data source last start address for video window ii 22 - 28 vprcc: chroma last start address for video window i 22 - 29 vprd0: chroma last start address for video window ii 22 - 29 vprd4: horizontal filter for video window i 22 - 29 vprd8: vertical filter for video window i 22 - 30 vprdc: horizontal filter for video window ii 22 - 30 vpre0: data source last start address for sub picture 22 - 31 vpre4: video window i source odd field start address 22 - 31 vpre8: video window i odd field chroma data source starting address 22 - 31 vprec: data source odd field last start address for video window i 22 - 32 vprf0: odd field chroma last start address for video window i 22 - 32 summary of registers (continued) page
crt processor registers 22 - 3 silicon motion ? , inc. SM731 confidential databook video processor control registers SM731 integrates a concurrent video processor. it can support 2 independent video windows using hardware scaling for any size of video windows at any location of the screen displa y. the video processor control registers specify the control registers for video processor. the video processor control registers can only be accessed through memory-mapped. vpr00: miscellaneous graphics and video control read/write address: 0800h power-on default: 00000000h this register specifies the controls for graphics and video window i/ii. (where x = don't care) bit 31 display off (doff) 0 = display on 1 = display off (except pop up icon) bit 30 reserved (r) (must be 0) bit 29 enable single pixel (esp) 0 = double pixel through video pipe 1 = single pixel through video pipe bit 28 current display field (field) (read only) 0 = current display even field 1 = current display odd field bit 27 reserved (r) bit 26 enable bob display (ebob) 0 = disable 1 = enable bit 25 enable separate data (video) to dac/tv and graphic data to write fifo. this bit needs to also be set to allow flicker reduction for tv display in index-color mode. (esd) 0 = disable 1 = enable bit 24 select video window i source start address same as video capture buffer start address. this bit is used to automatically display captured data on video window i without programming video window i source start address register (svwi). 0 = normal. video window i source start address is from vpr1c register. 1 = video window i source start address is equal to capture port buffer i source start address (vpr48) or capture port buffer ii source start address (vpr4c). if single buffer is selected for video capture, video 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 doff r esp field r ebob esd cvwi reserved gdt gde gdf 1514131211109876543210 tvws vwiic r vwiit vwiie vwiif vwic vwil vwit vwie vwif
22 - 4 crt processor registers silicon motion ? , inc. SM731 confidential databook window i source start address is equal to capture port buffer i source address. if double buffer is selected for video capture and capture port buffer i is busy, video window i source start address is equal to capture port buffer ii source address. bit 23:21 reserved bit 20 graphic data in tile format (gdt) 0 = normal format 1 = tile format bit 19 graphic enable (gde) 0 = disable 1 = enable bit 18:16 graphics data format (gdf) 000 = 8-bit index 001 = 15 -bit 5-5-5 rgb 010 = 16-bit 5-6-5 rgb 011 = 32-bit x-8-8-8 rgb 100 = 24-bit 8-8-8 rgb (packed) 101 = reserved 11x = reserved bit 15 top video window select (tvws) 0 = video window i is on top 1 = video window ii is on top bit 14 color key enable for video window ii (ckeii) 0 = disable 1 = enable bit 13 reserved (r) bit 12 video window ii data in tile format (vwiit) 0 = normal format 1 = tile format bit 11 video window ii enable (vwiie) 0 = disable 1 = enable bit 10:8 video window ii format (vwfii) 000 = 8-bit index 001 = 15-bit 5-5-5 rgb 010 = 16-bit 5-6-5 rgb 011 = 32-bit x-8-8-8 rgb 100 = 24-bit 8-8-8 rgb (packed) 101 = 8-bit 3-3-2 rgb 110 = yuv 4:2:2 111 = yuv 4:2:0 (uv interleave)
crt processor registers 22 - 5 silicon motion ? , inc. SM731 confidential databook bit 7 color key enable for video window i (ckei) 0 = disable 1 = enable bit 6:5 video window i line of filtering (vwil) 00 = 1 line 01 = 2 line 1x = 4 line (data format cannot be yuv 4:2:0 and bit 29 must set to 1) bit 4 video window i data in tile format (vwit) 0 = normal format 1 = tile format bit 3 video window i enable (vwie) 0 = disable 1 = enable bit 2:0 video window i format (vwif) 000 = 8-bit index 001 = 15-bit 5-5-5 rgb 010 = 16-bit 5-6-5 rgb 011 = 32-bit x-8-8-8 rgb 100 = 24-bit 8-8-8 rgb (packed) 101 = 8-bit 3-3-2 rgb 110 = yuv 4:2:2 111 = yuv 4:2:0 (uv interleave) vpr04: color keys read/write address: 0804h power-on default: undefined this register specifies color keys for the two video windows 8-bit color mode 16-bit color mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved video window ii color key index 151413121110987654 3210 reserved video window i color key index 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 video window ii color key [15:8] video window ii color key [7:0] 151413121110987654 3210 video window i color key [15:8] video window i color key [7:0]
22 - 6 crt processor registers silicon motion ? , inc. SM731 confidential databook 8-bit color mode 16-bit color mode 1 bit 31:24 reserved video window ii color key [15:8] bit 23:16 video window ii color key index video window ii color key [7:0] bit 15:8 reserved video window i color key [15:8] bit 7:0 video window i color key index video window i color key [7:0] note 1 : for 24-bit or 32-bit color mode, software will need to repack the color key data into rgb - 5:6:5 (16-bit) format. vpr08: color key masks read/write address: 0808h power-on default: undefined this register specifies color key masks for the two video window. bit 31:16 video window ii color key mask 0 = disable color mask 1 = enable color mask bit 15:0 video window i color key mask 0 = disable color mask 1 = enable color mask vpr0c: data source start address for extended graphics modes read/write address: 080ch power-on default: undefined this register specifies data source start address for extended graphics modes bit 31 graphic data status bit (gdsb) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 video window ii color key mask 151413121110987654 3210 video window i color key mask 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 gdsb reserved gdssa 151413121110987654 3210 gdssa
crt processor registers 22 - 7 silicon motion ? , inc. SM731 confidential databook bit 30:22 reserved bit 21:0 graphics data source starting address, in 64-bit segment (gdssa) vpr10: data source width and offset for extended graphics modes read/write address: 0810h power-on default: undefined this register specifies data source data line widt h and offset address for extended graphics modes. bit 31:26 reserved bit 25:16 graphics data source data line width, in 64-bit segment bit 15:10 reserved bit 9:0 graphics data start address offset, in 64-bit segment vpr14: video window i left and top boundaries read/write address: 0814h power-on default: undefined this register specifies left and top boundary for video window i. bit 31:27 reserved bit 26:16 video window i, top boundary bit 15:11 reserved bit 10:0 video window i, left boundary 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved graphics data source data line 151413121110987654 3210 reserved graphics data start address offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved video window i top boundary 151413121110987654 3210 reserved video window i left boundary
22 - 8 crt processor registers silicon motion ? , inc. SM731 confidential databook vpr18: video window i right and bottom boundaries read/write address: vp_base+18h power-on default: undefined this register specifies right and bottom boundary for video window i. bit 31:27 reserved bit 26:16 video window i, bottom boundary bit 15:11 reserved bit 10:0 video window i, right boundary vpr1c: video window i source start address read/write address: vp_base+1ch power-on default: undefined this register specifies video start address for video window i. bit 31 video window i status bit (vwis) bit 30:22 reserved bit 21:0 video window i source start address for, in 64-bit segment. (vwiss) vpr20: video window i source width and offset read/write address: vp_base+20h power-on default: undefined this register specifies video source data line width and offset address for video window i. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved video window i bottom boundary 151413121110987654 3210 reserved video window i right boundary 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 vwis reserved vwiss 151413121110987654 3210 vwiss
crt processor registers 22 - 9 silicon motion ? , inc. SM731 confidential databook bit 31:26 reserved bit 25:16 video window i source data line width, in 64-bit segment bit 15:10 reserved bit 9:0 video window i source address offset, in 64-bit segment vpr24: video window i stretch factor: read/write address: vp_base+24h power-on default: 00000000h this register specifies video horizontal and vertical stretch factor for video window i. for optimal display quality, we recommend destination to source ratio to be maximum of 4:1. the two high bytes of this register can be used to enable the ?bob? function. bit 31:24 video window ii initial odd field vertical scale factor bit 23:16 video window ii initial even field vertical scale factor vpr28: video window ii left and top boundaries read/write address: vp_base+28h power-on default: undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved video window i source data line 151413121110987654 3210 reserved video window i source address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 video window ii inital odd field v ideo window ii initial even field 151413121110987654 3210 video window i horizontal stretch video window i vertical stretch bit 15:8 video window 1 horizontal stretch factor (w1hsf) w1hsf = source destination * 256 note: when stretch factor is set to 0, it becomes a 1-to-1 stretch bit 7:0 video window 1 vertical stretch factor (w1vsf) note: when stretch factor is set to 0, it becomes a 1-to-1 stretch w1vsf = source destinatio n * 256
22 - 10 crt processor registers silicon motion ? , inc. SM731 confidential databook this register specifies left and top boundary for video window ii. bit 31:27 reserved bit 26:16 video window ii, top boundary bit 15:11 reserved bit 10:0 video window ii, left boundary vpr2c: video window ii right and bottom boundaries read/write address: vp_base+2ch power-on default: undefined this register specifies right and bottom boundary for video window ii. bit 31:27 reserved bit 26:16 video window ii, bottom boundary bit 15:11 reserved bit 10:0 video window ii, right boundary vpr30: video window ii source start address read/write address: vp_base+30h power-on default: undefined this register specifies video start address for video window ii. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved video window ii top boundary 151413121110987654 3210 reserved video window ii left boundary 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved video window ii bottom boundary 151413121110987654 3210 reserved video window ii right boundary
crt processor registers 22 - 11 silicon motion ? , inc. SM731 confidential databook bit 31 video window ii status bits (vwiis) bit 30:22 reserved bit 21:0 video window ii data source starting address (vwiids) vpr34: video window ii source width and offset read/write address: vp_base+34h power-on default: undefined this register specifies video source data line width and offset address for video window ii. bit 31:26 reserved bit 25:16 video window ii source data line width, in 64-bit segment bit 15:10 reserved bit 9:0 video window ii source address offset, in 64-bit segment vpr38: video window ii stretch factor read/write address: vp_base+38h/3?5h, index f8, f9, fa, fb power-on default: 00000000h this register specifies video horizontal and vertical stretch factor for video window ii. for optimal display quality, we recommend destination to source ratio to be maximum of 4:1. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 vwiis reserved vwiids 151413121110987654 3210 vwiids 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved video window ii source data line 151413121110987654 3210 reserved video window ii source address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 video window ii inital odd field v ideo window ii initial even field 151413121110987654 3210 video window ii horizontal stretch video window ii vertical stretch
22 - 12 crt processor registers silicon motion ? , inc. SM731 confidential databook bit 31:24 video window ii initial odd field vertical scale factor bit 23:16 video window ii initial even field vertical scale factor vpr3c: graphics and video control ii read/write: address: vp_base+3ch power-on default: 00000000h bit 31:24 sub picture horizontal filter 1 (shf1) bit 23:16 sub picture horizontal filter 0 (shf0) bit 15:13 reserved bit 12 color key control sub-picture (ckcs) 0 = disable 1 = enable* * only 8-bit and 16-bit sub-picture data format supported bit 11 sub-picture bi-linear enable (sbe) 0 = disable 1 = enable bit 10:9 sub-picture data format (sf) 00 = 8-bit alpha blending format (alpha_[3:0], color_[3:0]) 01 = 16-bit alpha blending format (alpha_[7:0], color_[7:0]) 1x = 32-bit alpha blending format (alpha_[7:0], color_[23:0]) bit 8 sub-picture enable (se) 0 = disable 1 = enable bit 15:8 video window ii horizontal stretch factor (w2hsf) w2hsf = source destination * 256 note: when stretch factor is set to 0, it becomes a 1-to-1 stretch bit 7:0 video window ii vertical stretch factor (w2vsf) note: when stretch factor is set to 0, it becomes a 1-to-1 stretch w2vsf = source destinatio n * 256 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 shf1 shf0 151413121110987654 3 2 1 0 reserved ckcs sbe sf se evwii uvs reserved evwii hb evwi uvs r evwi vb evwi hb
crt processor registers 22 - 13 silicon motion ? , inc. SM731 confidential databook bit 7 video window ii uv swap enable (evwiiuvs) 0 = disable 1 = enable bit 6:5 reserved bit 4 video window ii horizontal bi-linear enable (evwiihb) 0 = disable 1 = enable bit 3 video window i uv swap enable (evwiuvs) 0 = disable 1 = enable bit 2 reserved bit 1 video window i vertical bi-linear enable (evwivb) 0 = disable 1 = enable bit 0 video window i horizontal bi-linear enable (evwihb) 0 = disable 1 = enable vpr40: sub picture scale factor read/write address: vp_base+40h power-on default: 00000000h bit 31:24 sub picture initial odd field vertical scale factor bit 23:16 sub picture initial even field vertical scale factor 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 sub picture initial odd field vertical sub picture inital even field vertical 151413121110987654 3210 sub picture horizontal scale fact or sub picture vertical scale factor bit 15:8 sub picture horizontal scale factor ghsf = source destination * 256 bit 7:0 sub picture vertical scale factor gvsf = source destinatio n * 256
22 - 14 crt processor registers silicon motion ? , inc. SM731 confidential databook vpr44: sub picture scale factor lsb read/write address: vp_base+44h power-on default: 00000000h bit 31:24 sub picture initial odd field vertical scale factor lsb bit 23:16 sub picture initial even field vertical scale factor lsb vpr48: video window i chroma data source starting address read/write address: vp_base+48h power-on default: undefined bit 31:22 reserved bit 21:0 video window i chroma data source starting address (vwicsa) vpr4c: video window ii chroma data source starting address read/write address: vp_base+4ch power-on default: undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 sub picture initial odd field vertical lsb s ub picture inital even field vertical lsb 151413121110987654 3210 sub picture horizontal scale factor ls b sub picture vertical scale factor lsb bit 15:8 sub picture horizontal scale factor lsb ghsf = source destination * 65536 bit 7:0 sub picture vertical scale factor lsb gvsf = source destinatio n * 65535 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved vwicsa 151413121110987654 3210 vwicsa
crt processor registers 22 - 15 silicon motion ? , inc. SM731 confidential databook bit 31:22 reserved bit 21:0 video window ii chroma data source starting address (vwiicsa) vpr50: sub-picture data source starting address read/write address: vp_base=50h power-on default: undefined bit 31:22 reserved bit 21:0 sub-picture data source starting address vpr54: fifo priority control read/write address: vp_base+54h power-on default: 07216543h this register specifies fifo priority controls for graphics, flat panel read frame buffer fifo1, video window i, video window ii, flat panel write frame buffer, capture window an d flat panel read frame buffer fifo2. graphics fifo has the highest priority and flat panel read fifo2 has the lowest priority as default. bit 31:27 reserved (must be 0) bit 26:24 flat panel read fifo2 priority select (fpr fifo2 000 = request is off 001 = highest priority (1st) 010 = next priority (2nd) 011 = next priority (3rd) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved vwiicsa 151413121110987654 3210 vwiicsa 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub-picture data source 151413121110987654 3210 sub-picture data source 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved fpr fifo2 r cwfifo r fpw fifo 151413121110987654 3210 r vwii fifo r vwi fifo r fpr fifo1 r gfifo
22 - 16 crt processor registers silicon motion ? , inc. SM731 confidential databook 100 = next priority (4th) 101 = next priority (5th) 110 = next priority (6th) 111 = lowest priority (last) (default) bit 23 reserved (r) bit 22:20 capture window fifo priority select (cwfifo) 000 = request is off 001 = highest priority (1st) 010 = next priority (2nd) (default) 011 = next priority (3rd) 100 = next priority (4th) 101 = next priority (5th) 110 = next priority (6th) 111 = lowest priority (last) bit 19 reserved (r) bit 18:16 flat panel write fifo priority select (fpw fifo) 000 = request is off 001 = highest priority (1st) (default) 010 = next priority (2nd) 011 = next priority (3rd) 100 = next priority (4th) 101 = next priority (5th) 110 = next priority (6th) 111 = lowest priority (last) bit 15 reserved (r) bit14:12 video window ii fifo priority select (vwii fifo) 000 = request is off 001 = highest priority (1st) 010 = next priority (2nd) 011 = next priority (3rd) 100 = next priority (4th) 101 = next priority (5th) 110 = next priority (6th) (default) 111 = lowest priority (last) bit 11 reserved (r) bit 10:8 video window i fifo priority select (vwi fifo) 000 = request is off 001 = highest priority (1st) 010 = next priority (2nd) 011 = next priority (3rd) 100 = next priority (4th) 101 = next priority (5th) (default)
crt processor registers 22 - 17 silicon motion ? , inc. SM731 confidential databook 110 = next priority (6th) 111 = lowest priority (last) bit 7 reserved (r) bit 6:4 flat panel read fifo1 priority select (fpr fifo1) 000 = request is off 001 = highest priority (1st) 010 = next priority (2nd) 011 = next priority (3rd) 100 = next priority (4th) (default) 101 = next priority (5th) 110 = next priority (6th) 111 = lowest priority (last) bit 3 reserved bit 2:0 graphics fifo priority select (gfifo) 000 = request is off 001 = highest priority (1st) 010 = next priority (2nd) 011 = next priority (3rd) (default) 100 = next priority (4th) 101 = next priority (5th) 110 = next priority (6th) 111 = lowest priority (last) vpr58: fifo empty request level control read/write address: vp_base+58h power-on default: 00004444h this register specifies fifo empty request level for graphics fifo, video window i, and video window ii. at the specified empty fifo level, fifo request will be generated. default fifo empty levels are all 6 or more empty. for lcd read fifo1/fifo2 and lcd write fifo request level controls, they are located in fpr4a register. bit 31:15 reserved bit 14:12 sub picture fifo empty request level select (s fifo) 00x = 2 or more empty 010 = 2 or more empty 011 = 3 or more empty 100 = 4 or more empty (default) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 151413121110987654 3210 r s fifo r vwii fifo r vwi fifo r gfifo
22 - 18 crt processor registers silicon motion ? , inc. SM731 confidential databook 101 = 5 or more empty 11x = 6 or more empty bit 7 reserved (r) bit 10:8 video window ii fifo empty request level select (vwii fifo) 000 = 2 or more empty 001 = 4 or more empty 010 = 5 or more empty 011 = 6 or more empty 100 = 7 or more empty (default) 101 = 8 or more empty 110 = 10 or more empty 111 = 12 or more empty bit 7 reserved (r) bit 6:4 video window i fifo empty request level select (vwi fifo) 000 = 2 or more empty 001 = 4 or more empty 010 = 5 or more empty 011 = 6 or more empty 100 = 7 or more empty (default) 101 = 8 or more empty 110 = 10 or more empty 111 = 12 or more empty bit 3 reserved (r) bit 2:0 graphics fifo empty request level select (gfifo) 000 = 2 or more empty 001 = 4 or more empty 010 = 5 or more empty 011 = 6 or more empty 100 = 7 or more empty (default) 101 = 8 or more empty 110 = 10 or more empty 111 = 12 or more empty vpr5c: yuv to rgb conversion constant read/write address: vp_base+5ch power-on default: edededh this register specifies the yuv to rgb conversion constant.
crt processor registers 22 - 19 silicon motion ? , inc. SM731 confidential databook bit 31:24 luma y adjustment bit 23:16 red conversion constant bit 15:8 green conversion constant bit 7:0 blue conversion constant vpr60: current scan line position read only address: vp_base+60h power-on default: undefined this register specifies the current scan line position. bit 31:11 reserved bit 10:0 current scan line. this register re turns the number for current scan line. vpr64: signature analyzer control and status read/write address: vp_base+64h power-on default: undefined this register specifies controls and status for signature analyzer as well as the analyzer signature. bit 31:16 analyzer signature. these bits are ready only. bit 15:4 reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 luma y adjustment red conversion constant 151413121110987654 3210 green conversion constant blue conversion constant 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 151413121110987654 3210 reserved current scan line 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 analyzer signature 151413121110987654 3210 reserved sae sar sass
22 - 20 crt processor registers silicon motion ? , inc. SM731 confidential databook bit 3 signature analyzer enable/stop. software needs to set this bit = 1 as a "enable" control bit in order to enable signature analyzer. once the analysis is completed, the hardware will reset this bit = 0 as a "stop" status bit. (sae) 0 = stop (analysis is completed) 1 = enable (analysis is in progress) bit 2 signature analyzer reset/normal. software needs to set this bit = 1 as a (sar) "reset" control bit to reset signature shift register to "0" before turning on signature analyzer. in the next vertical sync pulse after bit 3 and bit 2 have been set to "11", bit 2 will be automatically reset to "0" as a "normal" status bit. 0 = normal (disable rese t to signature analyzer) 1 = reset (enable reset to signature analyzer) bit 1:0 signature analyzer source select. these bits select s the input source for the signature analyzer. (sass) 00 = source is red output from multimedia ramdac 01 = source is green output from multimedia ramdac 1x = source is blue output from multimedia ramdac vpr68: video window i scale factor lsb read/write address: vp_base+68h power-on default: 00000000h bit 31:24 video window i initial odd field vertical scale factor lsb bit 23:16 video window i initial even field vertical scale factor lsb vpr6c: video window ii scale factor lsb read/write address: vp_base+6ch power-on default: 00000000h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 vwi initial odd field vertical lsb vwi inital even field vertical lsb 151413121110987654 3210 vwi horizontal scale factor lsb vwi vertical scale factor lsb bit 15:8 video window i horizontal scale factor lsb ghsf = source destination * 65536 bit 7:0 video window i vertical scale factor lsb gvsf = source destinatio n * 65535
crt processor registers 22 - 21 silicon motion ? , inc. SM731 confidential databook bit 31:24 video window ii initial odd fiel d vertical scale factor lsb bit 23:16 video window ii initial even field vertical scale factor lsb vpr70: sub picture color look up register 0 read/write address: vp_base+70h power-on default: undefined bit 31:24 reserved bit 23:0 sub picture color look up register 0 vpr74: sub picture color look up register 1 read/write address: vp_base+74h power-on default: undefined bit 31:24 reserved bit 23:0 sub picture color look up register 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 vwii initial odd field vertical lsb vwii inital even field vertical lsb 151413121110987654 3210 vwii horizontal scale factor lsb vwii vertical scale factor lsb bit 15:8 video window ii horizontal scale factor lsb ghsf = source destination * 65536 bit 7:0 video window ii vertical scale factor lsb gvsf = source destinatio n * 65535 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture color look up 0 151413121110987654 3210 sub picture color look up 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture color look up 1 151413121110987654 3210 sub picture color look up 1
22 - 22 crt processor registers silicon motion ? , inc. SM731 confidential databook vpr78: sub picture color look up register 2 read/write address: vp_base+78h power-on default: undefined bit 31:24 reserved bit 23:0 sub picture color look up register 2 vpr7c: sub picture color look up register 3 read/write address: vp_base+7ch power-on default: undefined bit 31:24 reserved bit 23:0 sub picture color look up register 3 vpr80: sub picture color look up register 4 read/write address: vp_base+80h power-on default: undefined bit 31:24 reserved bit 23:0 sub picture color look up register 4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture color look up 2 151413121110987654 3210 sub picture color look up 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture color look up 3 151413121110987654 3210 sub picture color look up 3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture color look up 4 151413121110987654 3210 sub picture color look up 4
crt processor registers 22 - 23 silicon motion ? , inc. SM731 confidential databook vpr84: sub picture color look up register 5 read/write address: vp_base+84h power-on default: undefined bit 31:24 reserved bit 23:0 sub picture color look up register 5 vpr88: sub picture color look up register 6 read/write address: vp_base+88h power-on default: undefined bit 31:24 reserved bit 23:0 sub picture color look up register 6 vpr8c: sub picture color look up register 7 read/write address: vp_base+8ch power-on default: undefined bit 31:24 reserved bit 23:0 sub picture color look up register 7 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture color look up 5 151413121110987654 3210 sub picture color look up 5 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture color look up 6 151413121110987654 3210 sub picture color look up 6 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture color look up 7 151413121110987654 3210 sub picture color look up 7
22 - 24 crt processor registers silicon motion ? , inc. SM731 confidential databook vpr90: sub picture color look up register 8 read/write address: vp_base+90h power-on default: undefined bit 31:24 reserved bit 23:0 sub picture color look up register 8 vpr94: sub picture color look up register 9 read/write address: vp_base+94h power-on default: undefined bit 31:24 reserved bit 23:0 sub picture color look up register 9 vpr98: sub picture color look up register a read/write address: vp_base+98h power-on default: undefined bit 31:24 reserved bit 23:0 sub picture color look up register a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture color look up 8 151413121110987654 3210 sub picture color look up 8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture color look up 9 151413121110987654 3210 sub picture color look up 9 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture color look up a 151413121110987654 3210 sub picture color look up a
crt processor registers 22 - 25 silicon motion ? , inc. SM731 confidential databook vpr9c: sub picture color look up register b read/write address: vp_base+9ch power-on default: undefined bit 31:24 reserved bit 23:0 sub picture color look up register b vpra0: sub picture color look up register c read/write address: vp_base+a0h power-on default: undefined bit 31:24 reserved bit 23:0 sub picture color look up register c vpra4: sub picture color look up register d read/write address: vp_base+a4h power-on default: undefined bit 31:24 reserved bit 23:0 sub picture color look up register d 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture color look up b 151413121110987654 3210 sub picture color look up b 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture color look up c 151413121110987654 3210 sub picture color look up c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture color look up d 151413121110987654 3210 sub picture color look up d
22 - 26 crt processor registers silicon motion ? , inc. SM731 confidential databook vpra8: sub picture color look up register e read/write address: vp_base+a8h power-on default: undefined bit 31:24 reserved bit 23:0 sub picture color look up register e vprac: sub picture color look up register f read/write address: vp_base+ach power-on default: undefined bit 31:24 reserved bit 23:0 sub picture color look up register f vprb0: sub picture top/left boundary read/write address: vp_base+b0h power-on default: undefined bit 31:27 reserved bit 26:16 sub picture top boundary bit 15:11 reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture color look up e 151413121110987654 3210 sub picture color look up e 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture color look up f 151413121110987654 3210 sub picture color look up f 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture top boundary 151413121110987654 3210 reserved sub picture left boundary
crt processor registers 22 - 27 silicon motion ? , inc. SM731 confidential databook bit 10:0 sub picture left boundary vprb4: sub picture bottom/right boundary read/write address: vp_base+b4h power-on default: undefined bit 31:27 reserved bit 26:16 sub picture bottom boundary bit 15:11 reserved bit 10:0 sub picture right boundary vprb8: sub picture source data address offset and line width read/write address: vp_base+b8h power-on default: undefined bit 31:26 reserved bit 25:16 sub picture source data line width bit 15:10 reserved bit 9:0 sub picture source data address offset vprc0: data source last start address for extended graphics modes read/write address: vp_base+c0h power-on default: 3fffff this register specifies data source last starting address for extended graphics modes. when the current line starting address equal or greater then the last start address, the current line starting address will remain the same until next vertica l sync. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture bottom boundary 151413121110987654 3210 reserved sub picture right boundary 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sub picture source data line 151413121110987654 3210 reserved sub picture source data address offset
22 - 28 crt processor registers silicon motion ? , inc. SM731 confidential databook bit 31:22 reserved bit 21:0 graphics data source last starting address, in 64-bit segment (gdslsa) vprc4: data source last start address for video window i read/write address: vp_base+c4h power-on default: 3fffff this register specifies data source last starting address for video window i. when the current line starting address equal or greater then the last start address, the current line starting address will remain the same until next vertical sync. bit 31:22 reserved bit 21:0 video window i source last starting address, in 64-bit segment (vwislsa) vprc8: data source last start address for video window ii read/write address: vp_base+c8h power-on default: 3fffff this register specifies data source last starting address for video window ii. when the current line starting address equal or greater then the last start address, the current line starting address will remain the same until next vertical sync. bit 31:22 reserved bit 21:0 video window ii source last starting address, in 64-bit segment (vwiislsa) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved gdslsa 151413121110987654 3210 gdslsa 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved vwislsa 151413121110987654 3210 vwislsa 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved vwiislsa 151413121110987654 3210 vwiislsa
crt processor registers 22 - 29 silicon motion ? , inc. SM731 confidential databook vprcc: chroma last start address for video window i read/write address: vp_base+cch power-on default: 3fffff this register specifies chroma last starting address for vi deo window i. when the current line starting address equal or greater then the last start address, the current line starting address will remain the same until next vertical sync. bit 31:22 reserved bit 21:0 video window i chroma last starting address, in 64-bit segment (vwiclsa) vprd0: chroma last start address for video window ii read/write address: vp_base+d0h power-on default: 3fffff this register specifies data source last starting address for vi deo window ii. when the current line starting address equal or greater then the last start address, the current line starting address will remain the same until next vertical sync. bit 31:22 reserved bit 21:0 video window ii chroma last starting address, in 64-bit segment (vwiiclsa) vprd4: horizontal filter for video window i read/write: address: vp_base+d4h power-on default: 000000h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved vwiclsa 151413121110987654 3210 vwiclsa 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved vwiiclsa 151413121110987654 3210 vwiiclsa
22 - 30 crt processor registers silicon motion ? , inc. SM731 confidential databook bit 31:24 reserved bit 23:16 video window i horizontal filter 2 (vwihf2) bit 15:8 video window i horizontal filter 1 (vwihf1) bit 7:0 video window i horizontal filter 0 (vwihf0) vprd8: vertical filter for video window i read/write: address: vp_base+d8h power-on default: 00000000h bit 31:24 video window i vertical filter 3 (vwivf3) bit 23:16 video window i vertical filter 2 (vwivf2) bit 15:8 video window i vertical filter 1 (vwivf1) bit 7:0 video window i vertical filter 0 (vwivf0) vprdc: horizontal filter for video window ii read/write: address: vp_base+dch power-on default: 000000h bit 31:24 reserved bit 23:16 video window ii horizontal filter 2 (vwiihf2) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved vwihf2 151413121110987654 3 2 1 0 vwihf1 vwihf0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 vwivf3 vwivf2 151413121110987654 3 2 1 0 vwivf1 vwivf0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved vwiihf2 151413121110987654 3 2 1 0 vwiihf1 vwiihf0
crt processor registers 22 - 31 silicon motion ? , inc. SM731 confidential databook bit 15:8 video window ii horizontal filter 1 (vwiihf1) bit 7:0 video window ii horizontal filter 0 (vwiihf0) vpre0: data source last start address for sub picture read/write address: vp_base+e0h power-on default: 3fffff this register specifies data source last starting address fo r sub picture. when the curren t line starting address equal or greater then the last start address, the current line starting address will remain the same until next vertical sync. bit 31:22 reserved bit 21:0 sub picture source last starting address, in 64-bit segment (sslsa) vpre4: video window i source odd field start address read/write address: vp_base+e4h power-on default: undefined this register specifies video odd field start address for video window i. bit 31:22 reserved bit 21:0 video window i odd field source start address for, in 64-bit segment. (vwioss) vpre8: video window i odd field chroma data source starting address read/write address: vp_base+e8h power-on default: undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sslsa 151413121110987654 3210 sslsa 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved vwioss 151413121110987654 3210 vwioss
22 - 32 crt processor registers silicon motion ? , inc. SM731 confidential databook bit 31:22 reserved bit 21:0 video window i odd field chroma data source starting address (vwiocsa) vprec: data source odd field last start address for video window i read/write address: vp_base+ech power-on default: 3fffff this register specifies odd field data source last starting a ddress for video window i. when the current line starting address equal or greater then the last start address, the current line starting address will remain the same until next vertical sync. bit 31:22 reserved bit 21:0 video window i odd field source last starting address, in 64-bit segment (vwislsa) vprf0: odd field chroma last start address for video window i read/write address: vp_base+f0h power-on default: 3fffff this register specifies odd field chroma last starting addr ess for video window i. when the current line starting address equal or greater then the last start address, the current line starting address will remain the same until next vertical sync. bit 31:22 reserved bit 21:0 video window i odd field chroma last starting address, in 64-bit segment (vwioclsa) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved vwiocsa 151413121110987654 3 2 1 0 vwiocsa 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved vwioslsa 151413121110987654 3210 vwioslsa 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved vwioclsa 151413121110987654 3210 vwioclsa
2d drawing engine registers 23 - 1 silicon motion ? , inc. SM731 confidential databook chapter 23: 2d drawing engine registers table 26: drawing engine & capture control registers quick reference summary of registers page drawing engine control registers dpr00: source y or k2 23 - 3 dpr02: source x or k1 23 - 3 dpr04: destination y or start y 23 - 4 dpr06: destination x or start x 23 - 5 dpr08: dimension y or error term 23 - 5 dpr0a: dimension x or vector length 23 - 6 dpr0c: rop and miscellaneous control 23 - 6 dpr0e: drawing engine commands and control 23 - 8 dpr10: source row pitch 23 - 9 dpr12: destination row pitch 23 - 10 dpr14: foreground colors 23 - 10 dpr18: background colors 23 - 11 dpr1c: stretch source height y 23 - 12 dpr1e: drawing engine data format and location format select 23 - 12 dpr20: color compare 23 - 13 dpr24: color compare masks 23 - 14 dpr28: bit mask 23 - 15 dpr2a: byte mask enable 23 - 15 dpr2c: scissors left and control 23 - 15 dpr2e: scissors top 23 - 16 dpr30: scissors right 23 - 16 dpr32: scissors bottom 23 - 16 dpr34: mono pattern low 23 - 17 dpr38: mono pattern high 23 - 17 dpr3c: xy addressing destination & source window widths 23 - 17 dpr40: source base address 23 - 18 dpr44: destination base address 23 - 18
23 - 2 2d drawing engine registers silicon motion ? , inc. SM731 confidential databook dpr48: alpha value for blending bitblt 23 - 19 summary of registers (continued) page
2d drawing engine registers 23 - 3 silicon motion ? , inc. SM731 confidential databook drawing engine control registers the drawing engine supports various drawing functions, including bresenham line draw, short stroke line draw, bitblt, rectangle fill, hostblt, rotation blit, and others. hardware clipping is supported by 4 registers, dpr2c-dpr32, which defines a rectangular clipping area. the drawing engine supports two types of format for its source and destination locations. one can specify location formats in x-y coordinate, where the upper le ft corner of the screen is defined to be (0,0); this method is referred as x-y addressing. also, one can specify the location format based on its position in the display memory sequentially from the first pixel of the visible data; this method is referred as de linear addressing. to select de linear addressing, one must set dpr1e bit [3:0] = 1111. all drawing engine control register s can be accessed via memory-mapped. dpr00: source y or k2 read/write address: dp_base+00h power-on default: undefined this register specifies the 12-bit source y position in x-y addressing mode, or low-order source address in de linear addressing mode (when dpr1e bit [3:0] = 11xxb). this register is also used to specify the 14-bit for k2 constant of bresenham line when dpr0e bit [3:0] = 0111b to select bresenham line command function. bit 15:0 source y for x-y addressing. in 24-bit packed modes, source y needs to be multiplied by 3. or high-order source address sa[23:12] for de linear addressing. low-order 12-bit are in dpr02. bresenham line (dpr0e bit [3:0] = 0111b) bit 15:14 reserved bit 13:0 axial diagonal constant (k2) = 2 * (min(|dx|,|dy|) - max(|dx|,|dy|)) dpr02: source x or k1 read/write address: dp_base+02h power-on default: undefined this register specifies the 12-bit source x position in x-y addressing mode, or low-order source address in linear addressing mode (when dpr1e bit [3:0] = 11xxb). this register is also used to specify the 14-bit for k1 constant of bresenham line when dpr0e bit [3:0] = 0111b to sel ect bresenham line command function. for hostblt write 1514131211109876543210 source y for x-y addressing 1514131211109876543210 reserved axial diagonal constant (k2)
23 - 4 2d drawing engine registers silicon motion ? , inc. SM731 confidential databook command function (when dpr0e bit [3:0] = 1000b), this register is also used to specify the 5-bit host mono source for alignment. bit 15:13 reserved bit 12:0 source x for x-y addressing mode. in 24-bit packed modes, source x needs to be multiplied by 3. or low-order source address sa [11:0] for de linear addressing mode. higher order 12-bit are in dpr00. note: for 24-bit color pattern, xs = (patxs * 3) logic_or (yd[2:0] *3, shift 3 bits to left) for 32-bit color pattern, xs = (patxs) logic_or (yd[2:0], shift 3 bits to left) bresenham line (dpr0e bit [3:0] = 0111b) bit 15:14 reserved bit 13:0 axial step constant (k1) = 2 * min (|dx|, |dy|) hostblt write (dpr0e bit [3:0] = 1000b) bit 15:5 reserved bit 4:0 host mono source alignment for 8, 16, or 32-bit color modes. for 24-bit color mode, software needs to adjust for alignment. (hmsa) dpr04: destination y or start y read/write address: dp_base+04h power-on default: undefined this register specifies the 12-bit destination y position in x-y addressing mode or higher-order destination address for de linear addressing mode (when dpr1e bit [3:0] = 11xxb). this re gister is also used to specify vector y start address for bresenham line when dpr0e bit [3:0] = 0111b to select bresenham line command function. 1514131211109876543210 reserved source x for x-y addressing 1514131211109876543210 reserved axial step constant k1 1514131211109876543210 reserved hmsa 1514131211109876543210 destination y or start y
2d drawing engine registers 23 - 5 silicon motion ? , inc. SM731 confidential databook bresenham line (dpr0e bit [3:0] = 0111b bit 15:0 destination y for x-y addressing. in 24-bit vector y start address packed modes, destination y needs to be multiplied by 3. or high-order 12 bits destination address da[23:12] for de linear addressing. dpr06: destination x or start x read/write address: dp_base+06h power-on default: undefined this register specifies 12-bit destination x position in x-y addressing mode or low-order 12-bit destination address in de linear addressing mode (when dpr1e bit [3:0] = 11xxb). this re gister is also used to specify vector x start address for bresenham line when dpr0e bit [3:0] = 0111b to select bresenham line command function. bit 15:13 reserved bresenham line (dpr0e bit [3:0] = 0111b bit 12:0 destination x for x-y addressing. in 24-bit vector x start address packed modes, destination x needs to be multiplied by 3. or low-order 12 bits destination address da[11:0] for de linear addressing. dpr08: dimension y or error term read/write address: dp_base+08h power-on default: undefined this register specifies the rectangle height or dimension y in pixels. when bresenham line command function is selected (dpr0e bit [3:0] = 0111b), this register specifies the vector error term. when short stroke line command function is selected (dpr0e bit [3:0] = 0110b), this register specifies the short stroke line length for non-horizontal short stroke line 1514131211109876543210 reserved destination x or start x 1514131211109876543210 reserved dimension y or error term short stroke (dpr0e bit [3:0] = 0110b) bresenham line (dpr0e bit [3:0] = 0111b) bit 15:13 reserved reserved reserved bit 12:0 dimension y short stroke length if not a horizontal line ( 0 or 180 ) (et)*
23 - 6 2d drawing engine registers silicon motion ? , inc. SM731 confidential databook * vector error term is determined based on the following logic: et = 2 * min (|dx|,|dy|) - max (|dx|,|dy|) if starting x > ending x. et = 2 * min (|dx|,|dy|) - max (|dx|,|dy|) -1 if starting x <= ending x. dpr0a: dimension x or vector length read/write address: dp_base+0ah power-on default: undefined this register specifies the rectangle width or dimension x in pixels. when bresenham line command function is selected (dpr0e bit [3:0] = 0111b), this register specifies the v ector length. when short stroke line command function is selected (dpr0e bit [3:0] = 0110b), this register specifies the short stroke line length for horizontal short stroke line. bit 15:13 reserved dpr0c: rop and miscellaneous control read/write address: dp_base+0ch power-on default: undefined this register specifies the rop2/rop3 select, rop2 source select, mono data format, pixel control, and 3 rop operands. bit 15 rop2 or rop3 select (rop) 0 = select rop3 1 = select rop2 bit 14 rop2 source select. this bit is only valid when bit 15 of this register is set to "1". (rops) 0 = rop2 source is not pattern 1 = rop2 source is pattern bit 13:12 mono data select. mono data format is used to op timize font performance. driver selects particular mono data format for particular font sizes. (mds) 1514131211109876543210 reserved dimension x or vector length . bresenham line (dpr0e bit [3:0] = 0111b) short stroke (dpr0e bit [3:0] = 0110b) bit 12:0 dimension x. in 24-bit packed mode, dimension x needs to be multiplied by 3. (note: dimension y does not need to be multiplied by 3) vector length = dmax + 1.where dmax is the dimension of vector length which is on the major axis. major axis is determined to be the axis which has longer length. short stroke length for horizontal short stroke line. (= 0 or = 180 ) 1514131211109876543210 rop rops mds err mpc pcts te rop3 reserved rop code
2d drawing engine registers 23 - 7 silicon motion ? , inc. SM731 confidential databook 00 = no packed mono data 01 = mono data packed at 8-bit 10 = mono data packed at 16-bit 11 = mono data packed at 32-bit bit 11 enable repeat rotation blt. this bit is only valid when dpr0e[3:0] = 1011b. (err) 0 = disable 1 = enable bit 10 matching pixel control. this bit is only valid when transparency is enabled (bit 8 of this register = 1) (mpc) 0 = matching pixel is opaque 1 = matching pixel is transparent bit 9 pixel control transparency select (pcts) 0 = source controls transparency 1 = destination controls transparency bit 8 transparency enable (te) 0 = disable 1 = enable bit 7:4 rop3 code 1 reserved bit 3:0 rop3 code 1 rop2 code 2 notes: 1 3 operands 256 operations rop codes table reference liste d below. for details on rop codes, please refer to the microsoft's device driver adaptation guide. 2 2 operands 16 operations rop codes table listed below: rop3 code bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pattern 11110000 source 11001100 destination 10101010 rop2 code bit 3 bit 2 bit 1 bit 0 rop2 code bit 3 bit 2 bit 1 bit 0 zero 0000 d * s 1000 ~(d+ s) 0 0 0 1 ~(d s) 1001 d * ~s 0010 d 1 0 1 0 ~ s 0 0 1 1 d + ~s 1 0 1 1 s * ~d 0100 s 1 1 0 0 ~d 0 1 0 1 s + ~d 1 1 0 1
23 - 8 2d drawing engine registers silicon motion ? , inc. SM731 confidential databook dpr0e: drawing engine commands and control read/write address: dp_base+0eh power-on default: undefined (except for bit 15 and bit 12 = 0) this register specifies the drawing engine command and control registers. bit 15 drawing engine activate (dea) 0 = idle (power-on default = 0) 1 = start activate drawing engine bit 14 pattern select (ps) 0 = mono pattern 1 = color pattern bit 13 destination x update enable (due) 0 = do not update destination x on completion of a drawing engine function 1 = update destination x on completion of a drawing engine function bit 12 drawing engine quick start enable. if this bit is set, drawing engine will be activated right after dimension x is provided. one does not need to activate the drawing engine by setting bit 15 = 1 if quick start is already enabled. (deqs) 0 = disable (power-on default = 0) 1 = enable bit 11 direction for short stroke line and bitblt for diagonal and vertical line, this bit needs to be set to "0". (ssl) bit 10 bresenham major axis (y) (bma) 0= major axis is x 1= major axis is y. for vertical line, this bit needs to be set. bit 9:8 x-step and y-step (xys) 00 = 0 degree transform d s 0110 d + s 1 1 1 0 ~(d * s) 0111 one 1 1 1 1 1514131211109876543210 dea ps due deqs ssl bma xys gse hbsc psb dece command functions bit 11 short stroke line direction bitblt direction 0 not horizontal left to right 1 horizontal right to left rop2 code bit 3 bit 2 bit 1 bit 0 rop2 code bit 3 bit 2 bit 1 bit 0
2d drawing engine registers 23 - 9 silicon motion ? , inc. SM731 confidential databook 01 = 90 degree (cw90) 11 = 180 degree 10 = 270 degree (ccw90) bit 7 graphics stretch enable (only for y direction) (gse) 0 = disable 1 = enable bit 6 host bitblt source color select (hbsc) 0 = source is color 1 = source is monochrome bit 5 last pixel select for bresenham line (psb) 0 = vector not draw last pixel 1 = vector draw last pixel bit 4 drawing engine capture enable (dece) 0 = normal operation. no hostblt capture operation. 1 = enable hostblt read capture operation bit 3:0 command functions 0000 = bitblt 0001 = rectangle fill 0010 = de-tile bitblt (screen screen) 0011 = trapezoid pattern fill 0100 = alpha blending bitblt 0101 = run length encoding (rle) strip draw 0110 = short stroke 0111 = bresenham line draw 1000 = host blt write 1001 = host blt read 1010 = host blt write from left_bottom 1011 = rotation blt 1100 = reserved 1101 = reserved 1110 = reserved 1111 = dma texture load dpr10: source row pitch read/write address: dp_base+10h power-on default: undefined this register specifies the source row offset in pixel unit for 8/16/32-bit color modes. in 24-bit color mode, source row offset needs to be multiplied by 3. 1514131211109876543210 reserved source row offset
23 - 10 2d drawing engine registers silicon motion ? , inc. SM731 confidential databook bit 15:13 reserved bit 12:0 source row offset. in 24-bit color mode, sour ce row offset needs to be multiplied by 3. dpr12: destination row pitch read/write address: dp_base+12h power-on default: undefined this register specifies the destination row offset in pixel unit for 8/16/32-bit color modes. in 24-bit color mode, destination row offset needs to be multiplied by 3. bit 15:13 reserved bit 12:0 destination row offset. in 24-bit color mode, destination row offset needs to be multiplied by 3. dpr14: foreground colors read/write address: dp_base+14h power-on default: undefined the register specifies the foreground graphics color for 8-bit color (dpr1e bit [5:4] = 00b), 16-bit color (dpr1e bit [5:4] = 01b), and 24-bit color (dpr1e bit [5:4] = 11b) modes. 8-bit color mode 16-bit color mode 24-bit color mode 1514131211109876543210 reserved destination row offset 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 reserved 1514131211109876543210 reserved foreground color 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 foreground color high byte foreground color low byte 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved foreground color red 1514131211109876543210 foreground color green foreground color blue
2d drawing engine registers 23 - 11 silicon motion ? , inc. SM731 confidential databook 32-bit color mode 8-bit color mode 16-bit color mode 24-bit color mode 32-bit color mode bit 31:24 reserved reserved reserved alpha component bit 23:16 reserved reserved foreground color red foreground color red bit 15:8 reserved foreground color high byte foreground color green foreground color green bit 7:0 foreground color foreground color low byte foreground color blue foreground color blue 8-bit index dpr18: background colors read/write address: dp_base+18h power-on default: undefined the register specifies the background graphics color for 8-bit color (dpr1e bit [5:4] = 00), 16-bit color (dpr1e bit [5:4] = 01), and 24-bit color (dpr1e bit [5:4] = 11) modes. note: in monochrome transparency mode (font operation), the background color needs to be programmed to equal to the invert of foreground color in dpr14. 8-bit color mode 16-bit color mode 24-bit color mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 foreground alpha foreground color red 1514131211109876543210 foreground color green foreground color blue 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 reserved background color 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 background color high byte background color green 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved background color red 1514131211109876543210 background color green background color blue
23 - 12 2d drawing engine registers silicon motion ? , inc. SM731 confidential databook 8-bit color mode 16-bit color mode 24-bit color mode 32-bit color mode bit 31:24 reserved reserved reserved background alpha bit 23:16 reserved reserved background color red background color red bit 15:8 reserved background color high byte background color green background color green bit 7:0 background color background color low byte background color blue background color blue 8-bit index dpr1c: stretch source height y read/write address: dp_base+1ch power-on default: undefined this register specifies the height of source block for stretch bitblt. bit 15:12 reserved bit 11:0 source y dimension for stretch blt. (only for y direction) dpr1e: drawing engine data format and location format select read/write address: dp_base+1eh power-on default: undefined the register specifies drawing engine source & destination locations select and data format. bit 15 reserved (r) bit 14 pattern xy overwrite select (xy) 0 = normal. drawing engine uses bit [13:8] as pa ttern address only when it is in linear addressing mode (bit [3:0] = 1111b] 1 = overwrite. drawing engine uses bit [13:8] as pattern address no matter what addressing mode it is in. bit 13:11 pattern start y address (yd [2:0]). this address is only valid if bit 14 = 1 or bit [3:0] = 11xxb (linear addressing). bit 10:7 pattern start x address (xd [2:0]). this address is only valid if bit 14 = 1 or bit [3:0] = 11xxb (linear addressing). it is based on the top left corner of sc reen as (0,0) coordinate address. rotation is needed 1514131211109876543210 reserved source y dimension for stretch blt 15141312111098765 4 3210 r xy pattern start y pattern start x r dedf drawing eng location
2d drawing engine registers 23 - 13 silicon motion ? , inc. SM731 confidential databook for pattern source if xd is non-zero. all 4 bits (bit 10:7) are used at 24bpp. only 3 bits (bit 9:7) are used at 8, 16, and 32 bpp. bit 6 reserved bit 5:4 drawing engine data format (dedf) 00 = 8-bit per pixel 01 = 16-bit per pixel 10 = 32-bit per pixel 11 = 24-bit per pixel (24-bit packed) bit 3:0 drawing engine locations (source and destination) format select. the drawing engine supports two types of format for its source and destination loca tions. one can specifies location format in x-y coordinate, where the upper left corner of the screen is defined to be (0,0); this method is referred as x- y addressing. also, one can specifies the location fo rmat based on its position in the display memory sequentially from the first pixel of the visible data; this method is referred as de linear addressing. this register selects the pixel width for x- y addressing and de linear addressing. 1111 = de linear addressing else = xy screen width depends on dpr3c register dpr20: color compare read/write address: dp_base+20h power-on default: undefined the register specifies the color compare for 8-bit color (dpr1e bit [5:4] = 00), 16-bit color (dpr1e bit [5:4] = 01), and 24-bit color (dpr1e bit [5:4] = 11) modes. note, in monochrome transparency mode for font operations, the color compare need s to be programmed to equal to the foreground color in dpr14. 8-bit color mode 16-bit color mode 24-bit color mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 reserved color compare 8-bit index 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 color compare high byte color compare low byte 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved color compare red 1514131211109876543210 color compare green color compare blue
23 - 14 2d drawing engine registers silicon motion ? , inc. SM731 confidential databook 8-bit color mode 16-bit color mode 24-bit color mode bit 31:24 reserved reserved reserved bit 23:16 reserved reserved color compare red bit 15:8 reserved color compare high byte color compare green bit 7:0 color compare 8-bit index color compare low byte color compare blue dpr24: color compare masks read/write address: dp_base+24h power-on default: undefined the register specifies the color compare mask for 8-bit color (dpr1e bit [5:4] = 00), 16-bit color (dpr1e bit [5:4] = 01), and 24-bit color (dpr1e bit [5:4] = 11) modes. 8-bit color mode 16-bit color mode 24-bit color mode 8-bit color mode 16-bit color mode 24-bit color mode bit 31:24 reserved reserved reserved bit 23:16 reserved reserved color compare mask red 8-bit color mode 16-bit color mode 24-bit color mode bit 15:8 reserved color compare mask high byte color compare mask green bit 7:0 color compare mask color compare mask low byte color compare mask blue 8-bit index 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 reserved color compare 8-bit index 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 color compare mask high byte color compare mask low byte 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved color compare mask red 1514131211109876543210 color compare mask green color compare mask blue
2d drawing engine registers 23 - 15 silicon motion ? , inc. SM731 confidential databook dpr28: bit mask read/write address: dp_base+28h power-on default: undefined the register specifies the bit mask for 8-bit color (dpr1e bit [5:4] = 00) and 16-bit color (dpr1e bit [5:4] = 01) modes. 8-bit color mode 16-bit color mode 8-bit color mode 16-bit color mode bit 15:8 reserved bit mask high byte bit 7:0 bit mask 8-bit index bit mask low byte dpr2a: byte mask enable read/write address: dp_base+2ah power-on default: undefined the register specifies the byte mask enable register for 64-bit datapath. bit 15:0 byte mask for 128-bit datapath. each bit enables the corresponding byte data. 0 = disable write 1 = enable write dpr2c: scissors left and control read/write address: dp_base+2ch power-on default: undefined the register specifies the scissors left boundary and control registers. bit 15 reserved (r) 1514131211109876543210 reserved bit mask 8-bit index 1514131211109876543210 bit mask high byte bit mask low byte 1514131211109876543210 byte mask for 64-bit datapath 1514131211109876543210 r sbs se scissors boundary left
23 - 16 2d drawing engine registers silicon motion ? , inc. SM731 confidential databook bit 14 scissors boundary select (sbs) 0 = write disable outside the scissors boundary 1 = write disable inside the scissors boundary bit 13 scissors enable (se) 0 = disable 1 = enable bit 12:0 scissors boundary left. in 24-bit color mode, the scissors boundary left position needs to be multiplied by 3. dpr2e: scissors top read/write address: dp_base+2eh power-on default: undefined the register specifies the scissors top boundary. bit 15:0 scissors boundary top. in 24-bit color mode, the scissors boundary top position needs to be multiplied by 3. dpr30: scissors right read/write address: dp_base+30h power-on default: undefined the register specifies the right boundary. bit 15:13 reserved bit 12:0 scissors boundary right. in 24-bit color mode, the scissors boundary right position needs to be multiplied by 3. dpr32: scissors bottom read/write address: dp_base+32h power-on default: undefined the register specifies the bottom boundary. 1514131211109876543210 scissors boundary top 1514131211109876543210 reserved scissors boundary right
2d drawing engine registers 23 - 17 silicon motion ? , inc. SM731 confidential databook bit 15:0 scissors boundary bottom. in 24-bit color mode, the scissors boundary bottom position = scissors boundary top position dpr2e [11:0] + height of the clipping window. dpr34: mono pattern low read/write address: dp_base+34h power-on default: undefined the register specifies the monochrome pattern lower double word. it is 32-bit access only. the higher 32-bit are in dpr38. bit 31:0 mono pattern top 4 lines. line 3 data is located in the most significant byte where as line 0 data is located in the least significant bye. dpr38: mono pattern high read/write address: dp_base+38h power-on default: undefined the register specifies the monochrome pattern higher do uble word. it is 32-bit access only. the lower 32-bit are in dpr34. bit 31:0 mono pattern last 4 lines. line 7 data is located in the most significant byte where as line 4 data is located in the least significant bye. dpr3c: xy addressing destination & source window widths read/write address: dp_base+3ch power-on default: undefined the register specifies the xy width for source and destination window. 1514131211109876543210 scissors boundary bottom 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mono pattern top 4 lines 1514131211109876543210 mono pattern top 4 lines 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mono pattern last 4 lines 1514131211109876543210 mono pattern last 4 lines
23 - 18 2d drawing engine registers silicon motion ? , inc. SM731 confidential databook bit 31:28 reserved bit 27:16 destination window width in pixel for xy addressing mode (max. = 4096 pixel) bit 15:12 reserved bit 11:0 source window width in pixel for xy addressing mode (max. = 4096 pixel) dpr40: source base address read/write address: dp_base+40h power-on default: undefined the register specifies the source base address in 64-bit unit (8 byte unit). bit 31:24 reserved bit 23:0 source base address dpr44: destination base address read/write address: dp_base+44h power-on default: undefined the register specifies the destination base address in 64-bit (8-byte) unit. bit 31:24 reserved bit 23:0 destination base address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved destination window width in pixel 1514131211109876543210 reserved source window width in pixel 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved source base address 1514131211109876543210 source base address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved destination base address 151413121110987654 3210 destination base address
2d drawing engine registers 23 - 19 silicon motion ? , inc. SM731 confidential databook dpr48: alpha value for blending bitblt read/write address: dp_base+48h power-on default: undefined the register specifies the bottom boundary. bit 15:8 reserved bit 7:0 alpha value used in alpha blending bitblt color = (src * alpha + (255 - alpha) * dst) * 257/64k 1514131211109876543210 reserved alpha value

video capture control registers 24 - 1 silicon motion ? , inc. SM731 confidential databook chapter 24: video capture control registers table 27: capture control registers quick reference summary of registers page capture processor control registers cpr00: capture port control 24 - 2 cpr04: video source clipping control 24 - 4 cpr08: video source capture size control 24 - 4 cpr0c: capture port buffer i source start address 24 - 5 cpr10: capture port buffer ii source start address 24 - 5 cpr14: capture port source offset address 24 - 6 cpr18: capture fifo empty request level control 24 - 6 cpr1c: reserved (internal use) 24 - 6 cpr20: tile conversion setting 24 - 7 cpr24: start-end address 24 - 8
24 - 2 video capture control registers silicon motion ? , inc. SM731 confidential databook capture processor control registers the capture processor control registers specify the contro l registers for capture processor the capture processor control registers can only be accessed through memory-mapped. cpr00: capture port control read/write address: cp_base+00h power-on default: 00h this register specifies the capture port which can be used for video capture and video playback. bit 31:25 reserved bit 22 href polarity (href) 0 = "high" active 1 = "low" active bit 21:20 enable horizontal filtering (ehf) 00 = no filtering 01 = 2-tap filtering 10 = 3-tap filtering 11 = 4-tap filtering bit 19:18 enable vertical reduction (evr) 00 = no reduction 01 = 2 to 1 reduction 10 = 4 to 1 reduction 11 = reserved bit 17:16 enable horizontal reduction (ehr) 00 = no reduction 01 = 2 to 1 reduction 10 = 4 to 1 reduction 11 = reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved fdms vref href ehf evr ehr 1514131211109876543210 vdi fse idce dbe cc fis is cbs cfo vis buf2 buf1 vce bit 24 field detect method select (fdms) 0 = falling edge of vsync 1 = rising edge of vsynct bit 23 vref polarity (vref) 0 = "high" active 1 = "low" active vref href href odd even rising edge
video capture control registers 24 - 3 silicon motion ? , inc. SM731 confidential databook bit 15:14 video capture input data format (vdi) 00 = yuv 4:2:2 01 = yuv 4:2:2 (with byte swapping) 10 = rgb 5:5:5 11 = rgb 5:6:5 bit 13:11 frame skip enable (fse) 000 = no skip 001 = skip every other frame 010 = skip even frame 011 = skip odd frame 100 = capture 2 and skip 1 frame 101 = capture 3 and skip 1 frame 110 = capture 1 and skip 2 frame 111 = capture 1 and skip 3 frame bit 10 interlace data capture enable (idce) 0 = disable (non-interlace) 1 = enable (interlace data. even field will be capture d into buffer1 and odd field will be captured into buffer2) when this bit is set to 1, double bu ffer mode needs to be also enabled (bit 9 =1). bit 9 double buffer enable (dbe) 0 = disable. use buffer1 addressed by vpr48. 1 = enable. use buffer1 and buffer2 addressed by vpr48 and vpr4c. bit 8 capture control (cc) 0 = continuous capture 1 = conditional capture. capture is controlled by bit 1 or bit 2 of this register. bit 7 field input status (read only) (fis) 0 = even field 1 = odd field bit 6 interlace status (read only) (is) 0 = non-interlace 1 = interlace bit 5 current buffer status (read only) (cbs) 0 = buffer 1 is the current buffer used 1 = buffer 2 is the current buffer used bit 4 current frame capture status (read only) (cfo) 0 = skip the current frame 1 = capture the current frame bit 3 vsync input status (read only) (vis) 0 = vsync pulse is inactive 1 = vsync pulse is active
24 - 4 video capture control registers silicon motion ? , inc. SM731 confidential databook bit 2 buffer 2 status/control bit. this bit is used for so ftware to read back the st atus of the current frame. software needs to preset this bit to 1 when programming the buffer 2 starting address in vpr4c. this bit can be set by drawing engine, and it can also be reset by video capture unit. if continuous capture is selected (bit 8 =0), this bit will be ignored. (buf2) 0 = idle or capture has completed 1 = capture in progress bit 1 buffer 1 status/control bit. this bit is used for so ftware to read back the st atus of the current frame. software needs to preset this bit to 1 when prog ramming the buffer 1 starting address in vpr48. this bit can be set by drawing engine, and it can also be reset by video capture unit. if continuous capture is selected (bit 8 =0), this bit will be ignored. (buf1) 0 = idle or capture has completed 1 = capture in progress bit 0 video capture enable. when video capture is enabled, all video port i/o pins except for "blank" pin will become input pins only. this bit can also be accessed through i/o register space 3?5, index ff, bit [0]. (vce) 0 = disable 1 = enable cpr04: video source clipping control read/write address: cp_base+04h power-on default: undefined this register specifies top and left clipping of video source. bit 31:26 reserved bit 25:16 video source top clipping, # of line to drop bit 15:10 reserved bit 9:0 video source left clipping, # of pixel to drop cpr08: video source capture size control read/write address: cp_base+08h power-on default: undefined this register specifies video source capture size. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved video source top clipping 151413121110987654 3210 reserved video source left clipping
video capture control registers 24 - 5 silicon motion ? , inc. SM731 confidential databook bit 31:27 reserved bit 26:16 video source height bit 15:11 reserved bit 10:0 video source width cpr0c: capture port buffer i source start address read/write address: cp_base+0ch power-on default: undefined this register specifies video source start address for buffer i of capture port. bit 31:21 reserved bit 20:0 capture port buffer i source start address, in 64-bit segment cpr10: capture port buffer ii source start address read/write address: cp_base+10h power-on default: undefined this register specifies video source start address for buffer ii of capture port. bit 31:21 reserved bit 20:0 capture port buffer ii source start address, in 64-bit segment. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved video source height 151413121110987654 3210 reserved video source width 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved capture port i 151413121110987654 3210 capture port i 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved capture port ii 151413121110987654 3210 capture port ii
24 - 6 video capture control registers silicon motion ? , inc. SM731 confidential databook cpr14: capture port source offset address read/write address: cp_base+14h power-on default: undefined this register specifies video source offset address for capture port. bit 31:11 reserved bit 10:0 capture port source address offset, in 64-bit segment cpr18: capture fifo empty request level control read/write address: cp_base+18h power-on default: 00000006h this register specifies capture fifo empty request level. at the specified empty fifo level, fifo request will be generated. default fifo empty levels are all 6 or more empty. bit 31:3 reserved bit 2:0 capture window fifo empty request level select 000 = 2 or more empty 001 = 3 or more empty 010 = 4 or more empty 011 = 5 or more empty 100 = 6 or more empty 101 = 8 or more empty 110 = 10 or more empty (default) 111 = 12 or more empty cpr1c: reserved (internal use) read/write address: cp_base+1ch power-on default: 00h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 151413121110987654 3210 reserved capture port source 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 151413121110987654 3210 reserved capture window
video capture control registers 24 - 7 silicon motion ? , inc. SM731 confidential databook bit 31:0 reserved linear to tile address conversion for cpu access in order to access the frame buffer in tile mode during the time application software has no idea about the tile format in the memory. internal hardware has to make the address conversion to address to the right tile location. cpr20: tile conversion setting read/write address: cp_base+20h power-on default: 00h bit 31:6 reserved bit 5:3 resolution 000 = 640 x 480 001 = 800 x 600 010 = 1024 x 768 011 = 1280 x 1024 100 = 1600 x 1200 else = reserved bit 2 pixel size (ps) 0 = 16 bits per pixel 1 = 32 bits per pixel bit 1 tile mode (tm) 0 = read/write in linear mode. 1 = read/write in tile mode. bit 0 enable linear to tile conversion (el) 0 = disable tile conversion (default) 1 = enable tile conversion 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 151413121110987654 3210 reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 151413121110987654 3210 reserved resolution ps tm el
24 - 8 video capture control registers silicon motion ? , inc. SM731 confidential databook cpr24: start-end address read/write address: cp_base+24h power-on default: 00h start/end address of the range needed to do tile conversion. bit 31 reserved (r) bit 30:16 end address in 1k-byte as a unit (=byte address_[24:10]) bit 15 reserved bit 14:0 start address in 1k-byte as a unit (=byte address_[24:10]) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r end address 151413121110987654 3210 r start address
pci/agp dma control registers 25 - 1 silicon motion ? , inc. SM731 confidential databook chapter 25: pci/agp dma control registers table 28: motion comp video registers quick reference summary of registers page motion comp bus master cmd control registers mcr00: motion comp enable 25 - 3 mcr04: slot 0 y data source 25 - 3 mcr08: slot1 y data source 25 - 3 mcr0c: slot2 y data source 25 - 3 mcr10: slot3 y data source 25 - 4 mcr14: slot0 uv interleave data source 25 - 4 mcr18: slot1 uv interleave data source 25 - 4 mcr1c: slot2 uv interleave 25 - 5 mcr20: slot3 uv interleave data source 25 - 5 mcr24: y data source line offset 25 - 5 mcr28: uv interleave data source line offset 25 - 6 motion compensation icmd control registers table of entry register 25 - 6 physical address register 25 - 6 blocksize register 25 - 7 entire transfer size of 32-bit data 25 - 7 transfer size remaining 25 - 8 motion compensation idct control registers table of entry register 25 - 8 physical address register 25 - 8 blocksize register 25 - 9 entire transfer size of 32-bit data 25 - 9 transfer size remaining 25 - 10 host master control registers table of entry register 25 - 10 physical address register 25 - 10 blocksize register 25 - 11
25 - 2 pci/agp dma control registers silicon motion ? , inc. SM731 confidential databook entire transfer size of 32-bit data 25 - 11 transfer size remaining 25 - 12 starting address 25 - 12 width and offset 25 - 12 plane selection 25 - 13 texture 3d bus master control registers table of entry register 25 - 13 physical address register 25 - 14 blocksize register 25 - 14 entire transfer size of 32-bit data 25 - 14 transfer size remaining 25 - 15 summary of registers (continued) page
pci/agp dma control registers 25 - 3 silicon motion ? , inc. SM731 confidential databook motion comp bus master cmd control registers mcr00: motion comp enable read/write address: mcr_base + offset power-on default: bit 7:1 reserved bit 0 motion comp enable (mce) mcr04: slot 0 y data source read/write address: mcr_base + offset power-on default: bit 31:20 reserved bit 19:0 slot0, y data source starting address mcr08: slot1 y data source read/write address: mcr_base + offset power-on default: bit 31:20 reserved bit 19:0 slot1, y data source starting address mcr0c: slot2 y data source read/write address: mcr_base + offset 76543210 reserved mce 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved slot0 y data 1514131211109876543210 slot0 y data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved slot1 y data 1514131211109876543210 slot1 y data
25 - 4 pci/agp dma control registers silicon motion ? , inc. SM731 confidential databook power-on default: bit 31:20 reserved bit 19:0 slot2, y data source starting address mcr10: slot3 y data source read/write address: mcr_base + offset power-on default: bit 31:20 reserved bit 19:0 slot3, y data source starting address mcr14: slot0 uv interleave data source read/write address: mcr_base + offset power-on default: bit 31:20 reserved bit 19:0 slot0, uv interleave data source starting address mcr18: slot1 uv interleave data source read/write address: mcr_base + offset power-on default: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved slot2 y data 1514131211109876543210 slot2 y data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved slot3 y data 1514131211109876543210 slot3 y data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved slot0 uv interleave 1514131211109876543210 slot0 uv interleave
pci/agp dma control registers 25 - 5 silicon motion ? , inc. SM731 confidential databook bit 31:20 reserved bit 19:0 slot1, uv interleave data source starting address mcr1c: slot2 uv interleave read/write address: mcr_base + offset power-on default: bit 31:20 reserved bit 19:0 slot2, uv interleave data source starting address mcr20: slot3 uv interleave data source read/write address: mcr_base + offset power-on default: bit 31:20 reserved bit 19:0 slot3, uv interleave data source starting address mcr24: y data source line offset read/write address: mcr_base + offset power-on default: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved slot1 uv interleave 1514131211109876543210 slot1 uv interleave 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved slot2 uv interleave 1514131211109876543210 slot2 uv interleave 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved slot3 uv interleave 1514131211109876543210 slot3 uv interleave
25 - 6 pci/agp dma control registers silicon motion ? , inc. SM731 confidential databook bit 8:0 y data source line offset (row pitch) mcr28: uv interleave data source line offset read/write address: mcr_base + offset power-on default: bit 8:0 uv interleave data source line offset (row pitch) motion compensation icmd control registers table of entry register read/write address: icmd_reg_base + offset offset 0: power-on default: xxh bit 31:2 table of entry address bit 1 don?t care (dc) bit 0 link list bit (ll) 1 = more table of entries 0 = end of table of entry physical address register read/write address: icmd_reg_base + offset offset 4: power-on default: xxh 76543210 offset 76543210 uv interleave data source line offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 table of entry 1514131211109876543210 table of entry dc ll
pci/agp dma control registers 25 - 7 silicon motion ? , inc. SM731 confidential databook bit 31:2 physical data memory address bit 1:0 don?t care blocksize register read/write address: icmd_reg_base + offset offset 8: power-on default: xxh bit 31:16 read only bit 15:0 block size entire transfer size of 32-bit data read/write address: icmd_reg_base + offset offset c: power-on default: 00h bit 31 enable master interface (emi) bit 30 use of physical memory data address instead of ta ble entry address during master request phase (pmd) bit 29:18 don?t care bit 17:0 entire transfer size (ets) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 physical data memory 1514131211109876543210 physical data memory don?t care 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 read only 1514131211109876543210 block size 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 emi pmd don?t care ets 1514131211109876543210 ets
25 - 8 pci/agp dma control registers silicon motion ? , inc. SM731 confidential databook transfer size remaining read/write address: icmd_reg_base + offset offset 10: read only power-on default: xxh bit 31:18 don?t care bit 17:0 remaining transfer size including all blocks (rts) motion compensation idct control registers table of entry register read/write address: idct_reg_base + offset offset 0: power-on default: xxh bit 31:2 table of entry address bit 1 don?t care (dc) bit 0 link list bit (ll) 1 = more table of entries 0 = end of table of entry physical address register read/write address: idct_reg_base + offset offset 4: power-on default: xxh 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 don?t care rts 1514131211109876543210 rts 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 table of entry 1514131211109876543210 table of entry dc ll
pci/agp dma control registers 25 - 9 silicon motion ? , inc. SM731 confidential databook bit 31:2 physical data memory address bit 1:0 don?t care blocksize register read/write address: idct_reg_base + offset offset 8: power-on default: xxh bit 31:16 read only bit 15:0 block size entire transfer size of 32-bit data read/write address: idct_reg_base + offset offset c: power-on default: 00h bit 31 enable master interface (emi) bit 30 use of physical memory data address instead of ta ble entry address during master request phase (pmd) bit 29:18 don?t care bit 17:0 entire transfer size (ets) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 physical data memory 1514131211109876543210 physical data memory don?t care 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 read only 1514131211109876543210 block size 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 emi pmd don?t care ets 1514131211109876543210 ets
25 - 10 pci/agp dma control registers silicon motion ? , inc. SM731 confidential databook transfer size remaining read/write address: idct_reg_base + offset offset 10: read only power-on default: xxh bit 31:18 don?t care bit 17:0 remaining transfer size including all blocks (rts) host master control registers table of entry register read/write address: host master control_reg_base + offset offset 0: power-on default: xxh bit 31:2 table of entry address bit 1 don?t care (dc) bit 0 link list bit (ll) 1 = more table of entries 0 = end of table of entry physical address register read/write address: host master control_reg_base + offset offset 4: power-on default: xxh 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 don?t care rts 1514131211109876543210 rts 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 table of entry 1514131211109876543210 table of entry dc ll
pci/agp dma control registers 25 - 11 silicon motion ? , inc. SM731 confidential databook bit 31:2 physical data memory address bit 1:0 don?t care blocksize register read/write address: host master control_reg_base + offset offset 8: power-on default: xxh bit 31:16 read only bit 15:0 block size entire transfer size of 32-bit data read/write address: host master control_reg_base + offset offset c: power-on default: 00h bit 31 enable master interface (emi) bit 30 use of physical memory data address instead of ta ble entry address during master request phase (pmd) bit 29:18 don?t care bit 17:0 entire transfer size (ets) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 physical data memory 1514131211109876543210 physical data memory don?t care 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 read only 1514131211109876543210 block size 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 emi pmd don?t care ets 1514131211109876543210 ets
25 - 12 pci/agp dma control registers silicon motion ? , inc. SM731 confidential databook transfer size remaining read/write address: host master control_reg_base + offset offset 10: read only power-on default: xxh bit 31:18 don?t care bit 17:0 remaining transfer size including all blocks (rts) motion compensation icmd control registers starting address read/write address: host master control_reg_base + offset offset 14: power-on default: undefined bit 31:20 reserved bit 19:0 starting address for master transfer width and offset read/write address: host master control_reg_base + offset offset 18: power-on default: undefined bit 31:26 reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 don?t care rts 1514131211109876543210 rts 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved starting address 1514131211109876543210 starting address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved width for master transfer 1514131211109876543210 reserved offset for master transfer
pci/agp dma control registers 25 - 13 silicon motion ? , inc. SM731 confidential databook bit 25:16 width for master transfer bit 15:10 reserved bit 9:0 offset for master transfer plane selection read/write address: host master control_reg_base + offset offset 1c: power-on default: 00 bit 31:3 reserved bit 2 enable y-plane transfer bit 1 enable u-plane transfer bit 0 enable v plane transfer texture 3d bus master control registers table of entry register read/write address: text3d_reg_base + offset offset 0: power-on default: xxh bit 31:2 table of entry address bit 1 don?t care (dc) bit 0 link list bit (ll) 1 = more table of entries 0 = end of table of entry 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 reserved ey eu ev 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 table of entry 1514131211109876543210 table of entry dc ll
25 - 14 pci/agp dma control registers silicon motion ? , inc. SM731 confidential databook physical address register read/write address: text3d_reg_base + offset offset 4: power-on default: xxh bit 31:2 physical data memory address bit 1:0 don?t care blocksize register read/write address: text3d_reg_base + offset offset 8: power-on default: xxh bit 31:16 read only bit 15:0 block size entire transfer size of 32-bit data read/write address: text3d_reg_base + offset offset c: power-on default: 00h bit 31 enable master interface (emi) bit 30 use of physical memory data address instead of ta ble entry address during master request phase (pmd) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 physical data memory 1514131211109876543210 physical data memory don?t care 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 read only 1514131211109876543210 block size 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 emi pmd don?t care ets 1514131211109876543210 ets
pci/agp dma control registers 25 - 15 silicon motion ? , inc. SM731 confidential databook bit 29:18 don?t care bit 17:0 entire transfer size (ets) transfer size remaining read/write address: text3d_reg_base + offset offset 10: read only power-on default: xxh bit 31:18 don?t care bit 17:0 remaining transfer size in cluding all blocks (rts) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 don?t care rts 1514131211109876543210 rts

tv encoder registers 26 - 1 silicon motion ? , inc. SM731 confidential databook chapter 26: tv encoder registers table 29: tv encoder registers quick reference summary of registers page common register mode register 26 - 2 closed captioning registers closed captioning enable register 26 - 2 closed captioning line number register 26 - 3 closed captioning 1st and 2nd byte data for odd field 26 - 3 closed captioning 1st and 2nd byte data for even field 26 - 4 closed captioning status register 26 - 4
26 - 2 tv encoder registers silicon motion ? , inc. SM731 confidential databook tv decoder register descriptions the following are the descriptions for each registers. common register mode register read/write address: 60h power-on default: 00h this register controls main function as follows. bit 7:6 don?t care. these bits are permanently set to logic 0 bit 5 genlock control (gl) this bit controls genlock on/off. when the genlock is on, sub-carrier is aligned by the horizontal sync for every four or eight fields. 0: on 1: off bit 4 override control (ov) this bit switches the video mode select source. 0: mode pins are selected 1: mode register bits are selected bit 3 blank level control (bl) this bit switches are the black setup level 0: black level is 7.5 ire 1: black level is 0 ire bit 2:0 video mode select these bits switch the video mode when (ov) is 1. 000: ntsc ccir 001: ntsc square pixel 010: ntsc 4fsc 100: pal ccir 101: pal square pixel closed captioning registers closed captioning enable register read/write address: 61h power-on default: 00h 76543210 don?t care gl ov bl video mode
tv encoder registers 26 - 3 silicon motion ? , inc. SM731 confidential databook this register controls the closed captioning function on/off as follows. if this function is enabled and a new data is not written (the field status is 1), a null data (80 hex) will be output. bit 7:2 don?t care. these bits are permanently set to logic 0 bit 1:0 closed captioning enable (cce) these bits control the closed captioning on/off for each field 00: disable 01: enable odd field only 10: enable even field only 11: enable both fields closed captioning line number register read/write address: 62h power-on default: 11h this register controls closed captioning line number as follows: bit 7:5 don?t care. these bits are permanently set to logic 0 bit 4:0 closed captioning line number select these bits set the line number for the closed captioning data. for ntsc mode, the actual line number will be ccl + 4 and ccl +263 +4 for pal mode, the actual line number will be ccl +1 and ccl + 313+1 closed captioning 1st and 2nd byte data for odd field read/write address: 63h power-on default: 00h bit 7:0 closed captioning 1st byte odd field read/write address: 64h power-on default: 00h 76543210 don?t care cce 76543210 don?t care closed captioning line number 76543210 closed captioning 1st byte odd field
26 - 4 tv encoder registers silicon motion ? , inc. SM731 confidential databook bit 7:0 closed captioning 2nd byte odd field the value at closed captioning 1st byte will be output as a 1st closed captioning data of the odd filed, and the value at closed captioning 2nd byte will be output as a 2nd one. when one of these bytes is written, the odd status bit ost will be cleared. closed captioning 1st and 2nd byte data for even field read/write address: 65h power-on default: 00h bit 7:0 closed captioning 1st byte even field read/write address: 66h power-on default: 00h bit 7:0 closed captioning 2nd byte even field the value at closed captioning 1st byte will be output as a 1st closed captioning data of the even filed, and the value at closed captioning 2nd byte will be output as a 2nd one. when one of these bytes is written, the even status bit est will be cleared. closed captioning status register read only address: 67h power-on default: 03h this register shows the closed captioning status of each field. if these bits are set to 1, existed data was sent out, and suitable for writing a new data to each closed captioning data registers. these bits are cleared on new data writing for each field bit 7:2 don?t care. these bits are permanently set to logic 0 76543210 closed captioning 2nd byte odd field 76543210 closed captioning 1st byte even field 76543210 closed captioning 2nd byte even field 76543210 don?t care ost est
tv encoder registers 26 - 5 silicon motion ? , inc. SM731 confidential databook bit 1 closed captioning odd filed status (ost) this bit shows the odd field status. when set to 1, the data was sent out. 0: the data is not sent 1: the data is sent and ready for writing next data bit 0 closed captioning even field status (est) this bit shows the even field status. when set to 1, the data was sent out. 0: the data is not sent 1: the data was sent and ready for writing next data.

3d registers 27 - 1 silicon motion ? , inc. SM731 confidential databook chapter 27: 3d registers table 30: 3d registers addr register name comment 100 device 0 104 primitive type 108 zw_reg 10c stencil_reg 110 z_init_value 114 pixel_reg 118 texture_factor 11c fog color 120 fb_zb_stride 124 z base address in qdw unit 128 3d display address 3d display address 12c drawbufferbaseaddr in qdw (128-bit) 130 clip top_left 134 clip bottom_right 138 window size 13c zw norm_1 wnear for w buf; 140 zw norm_2 (2^n - 1)/ (wfar - wnear), n=16 scale value when in z buf 144 fog norm_1 w1 148 fog norm_2 255/(w2 - w1) 150 154 158 15c 160 *text0_bump_envreg 164 text0_bump_envmat 168 text0_border_color 16c text0 color key1 170 text0 color key2 174 text0_blend_reg 178 t0_lod_textid 17c text0_register 180 t0_lvl0_base [31] agp [30] flush cache [24:0] in 128_byte 184 t0_lvl1_base 188 t0_lvl2_base 18c t0_lvl3_base 190 t0_lvl4_base 194 t0_lvl5_base 198 t0_lvl6_base 19c t0_lvl7_base 1a0 t0_lvl8_base 1a4 t0_lvl9_base 1a8 t0_lvl10_base 1ac 1b0 text1_bump_envreg 1b4 text1_bump_envmat 1b8 text1_border_color 1bc text1 color key1 1c0 tex t 1 c o l o r key 2 1c4 text1_blend_reg 1c8 t1_lod_textid 1cc text1_register 1d0 t1_lvl0_base [31] agp [30] flush cache 1d4 t1_lvl1_base 1d8 t1_lvl2_base addr register name comment
27 - 2 3d registers silicon motion ? , inc. SM731 confidential databook 1dc t1_lvl3_base 1e0 t1_lvl4_base 1e4 t1_lvl5_base 1e8 t1_lvl6_base 1ec t1_lvl7_base 1f0 t1_lvl8_base 1f4 t1_lvl9_base 1f8 t1_lvl0_base 1fc addr register name comment table 1: vertex registers addr bit_[31:0] vertex 0 register addr bit_[31:0] vertex 1 register comments 400 32 x0 500 32 x1 ieee floating point 404 32 y0 504 32 y1 " 408 32 z0 508 32 z1 " 40c 32 w0 perspective correction 50c 32 w1 perspective correction " 410 32 diffuse color 510 32 diffuse color argb8888 414 32 specular color 514 32 specular color argb8888 418 32 u0_1st 518 32 u0_1st ieee floating point 41c 32 v0_1st 51c 32 v0_1st " 420 32 u0_2nd 520 32 u0_2nd " 424 32 v0_2nd 524 32 v0_2nd " 458 1 go at [0] 558 1 go at [0]
3d registers 27 - 3 silicon motion ? , inc. SM731 confidential databook table 31: global fog look up table (700-7ff) table 32: 3d registers quick reference addr bit_[31:0] vertex 2 register comments 600 32 x0 ieee floating point 604 32 y0 " 608 32 z0 " 60c 32 w0 perspective correction " 610 32 diffuse color argb8888 614 32 specular color argb8888 618 32 u0_1st ieee floating point 61c 32 v0_1st " 620 32 u0_2nd " 624 32 v0_2nd " 658 1 go at [0] global fog factor - look up table dpr700[31:0] fog3210 dpr704[31:0] fog7654 ??????.. dpr7fc[31:0] last 4 fogs (ff,fe,fd & fc) summary of registers page device 0 register (100) 27 - 5 primitive register (104) 27 - 6 zw_reg (108) 27 - 6 stencil register (10c) 27 - 7 z/w initial value (110) 27 - 8 pixel register (114) 27 - 9 texture factor (118) 27 - 11 fog color (11c) 27 - 11 fb_zb stride register (120) 27 - 11 z base address (124) 27 - 12 3d display address (128) 27 - 12 draw buffer base address (12c) 27 - 12
27 - 4 3d registers silicon motion ? , inc. SM731 confidential databook clip top left register (130) 27 - 13 clip bottom right register (134) 27 - 13 window size (138)* 27 - 13 zw norm_1 (13c) 27 - 14 zw norm_2 (140) 27 - 14 fog norm_1 (144) 27 - 14 fog norm_2 (148) 27 - 15 text_bump_env (160 & 1b0) 27 - 15 text_bump_env_mat (164 & 1b4) 27 - 15 texture border color (168 & 1b8) 27 - 16 texture color key 1 (16c & 1bc) 27 - 16 texture color key 2 (170 & 1c0) 27 - 16 texture blending register (174 & 1c4) 27 - 17 text0_lod_textid (178) & text1_lod_textid (1c8) 27 - 19 text0_reg (17c) & text1_reg (1cc) 27 - 19 text0_texture level 0 base address (180) & text1_texture level 0 base address(1d0) 27 - 21 texture level 1 base address (184 & 1d4) 27 - 21 texture level 2 base address (188 & 1d8) 27 - 22 texture level 3 base address (18c & 1dc) 27 - 22 texture level 4 base address (190 & 1e0) 27 - 22 texture level 5 base address (194 & 1e4) 27 - 22 texture level 6 base address (198 & 1e8) 27 - 22 texture level 7 base address (19c & 1ec) 27 - 22 texture level 8 base address (1a0& 1f0) 27 - 22 texture level 9 base address (1a4 & 1f4) 27 - 23 summary of registers (continued) page
3d registers 27 - 5 silicon motion ? , inc. SM731 confidential databook device 0 register (100) write only address: dp_base + 100h power-on default: undefined bit 31:18 reserved bit 17 enable performance counter (epc) bit 16 reset performance counter (rpc) bit 15 select crt vsync for flip control (crt) 0 = select lcd vsync (default) 1 = select crt vsync bit 14:13 reserved bit 12 enable internal sram self test. status report at device 1 status register bit 11 pe cache write b ack ahead enable bit 10 flip block enable (fbe) bit 9 z cache xy shift 4 bits enable (zcxy) bit 8 z cache write back ahead enable (zcwb) bit 7 z tile enable (zte) bit 6 draw buffer tile enable (dbte) bit 5 crt display address use 3d display address (crt) bit 4 panel display address use 3d display address (pda) bit 3 pe cache flush (texture cache flush = move to texture base bit [30]) (pe) bit 2 z map bypass (zmap) 0 = normal, zero cycle z op 1 = bypass bit 1 z initial enable (zie) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved epc rpc 1514131211109876543210 crt reserved sram pe fbe zcxy zcwb zte dbte crt pda pe zmap zie zcf
27 - 6 3d registers silicon motion ? , inc. SM731 confidential databook bit 0 z cache flush (zcf) primitive register (104) write only address: dp_base + 104h power-on default: undefined bit 31:13 reserved bit 12:10 *edge flag 000: no draw 001: v0 010: v1 100: v2 111: all else: reserved bit 9 *draw line (dl) 0: x major 1: y major bit 8:6 *vertex buffer type bit 5:2 *primitive type bit 1:0 cull type 00: no cull 01: cw 10: ccw 11: reserved zw_reg (108) write only address: dp_base + 108h power-on default: undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 reserved edge flag dl vertex type primitive type cull type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved z bias 1514131211109876543210 stencil write mask wb ze dbf zce zcf
3d registers 27 - 7 silicon motion ? , inc. SM731 confidential databook bit 31:21 reserved bit 20:16 z bias bit 15:8 stencil write mask bit 7 use w buffer (wb) 0: use z buffer 1: use w buffer bit 6 z update enable (ze) bit 5:4 depth buffer format (dbf) 00: 16 bit z only, no stencil 01: 32_bit, 24 bits z and 8 bits stencil bit 3 z compare enable (zce) 0: disable z 1: enable z compare bit 2:0 z compare function (zcf) 000:never 001:less 010:equal 011:lessequal 100:greater 101:not equal 110:greaterequal 111:always note: z supports 1) 16_bit fixed point without stencil. 2) 24_bit fixed point with 8_bit stencil. w supports 1) 16_bit fixed point wo stencil. 2) 24_bit floating point with 8_bit stencil. stencil register (10c) write only address: dp_base + 10ch power-on default: undefined bit 31:24 stencil mask bit 23:16 stencil reference register bit 15 reserved (r) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 stencil mask stencil reference register 1514131211109876543210 r stencil pass r stencil z fail r stencil fail sce scf
27 - 8 3d registers silicon motion ? , inc. SM731 confidential databook bit 14:12 stencil pass operations 000: keep 001: zero 010: replace 011: increment saturate 100: decrement saturate 101: invert 110: increment 111: decrement bit 11 reserved (r) bit 10:8 stencil z fail operations bit 7 reserved (r) bit 6:4 stencil fail operations bit 3 stencil compare enable (sce) bit 2:0 stencil compare function (scf) 000: never 001: less 010: equal 011: less equal 100: greater 101: not equal 110: greater equal 111:always z/w initial value (110) write only address: dp_base + 110h power-on default: undefined for 24-bit z fix point bit 31:24 stencil planes bit 23:0 fix point z 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 stencil planes fix point z 1514131211109876543210 fix point z
3d registers 27 - 9 silicon motion ? , inc. SM731 confidential databook for 16-bit z fix point bit 31:16 reserved bit 15:0 fixed point initial z value for 24-bit floating w bit 31:24 stencil planes bit 23:0 floating point w (se8m15) for 16-bit fix point w bit 31:16 reserved bit 15:0 fixed point w value note: stencil only supported in 24bit z or w pixel register (114) write only address: dp_base + 114h power-on default: undefined bit 31:28 process id 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 fixed point initial z value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 stencil planes floating point w 1514131211109876543210 floating point w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 fixed point w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 process id reserved pce se fbf sm source blending 1514131211109876543210 destination blending abe alpha test reserved ate de tft fe
27 - 10 3d registers silicon motion ? , inc. SM731 confidential databook bit 27:26 reserved bit 25 perspect correct enable (pce) when this bit set to 0, setup engine will force w = 1. bit 24 specular enable (se) bit 23:22 frame buffer format (fbf) 00: rgb565 01: argb1555 10: argb4444 11: argb8888 bit 21:20 shade mode (sm) 00: flat 01: gouraud 10: phong 11: reserved bit 19:16 source blending factor 0000 zero 0x0 0001 one 0x1 0010 srccolor 0x2 0011 invsrccolor 0x3 0100 srcalpha 0x4 0101 invsrcalpha 0x5 0110 destalpha 0x6 0111 invdestalpha 0x7 1000 destcolor 0x8 1001 invdestcolor 0x9 1010 srcalphasat 0xa 1011 bothsrcalpha 0xb 1100 bothinvsrcalpha 0xc bit 15:12 destination blending factor bit 11 alpha blend enable (abe) bit 10:8 alpha test function 000 never 0x0 001 less 0x1 010 equal 0x2 011 lessequal 0x3 100 greater 0x4 101 notequal 0x5 110 greaterequal 0x6 111 always 0x7 bit 7:4 reserved
3d registers 27 - 11 silicon motion ? , inc. SM731 confidential databook bit 3 alpha test enable (ate) bit 2 dithering enable (de) bit 1 table fog type (tft) 0: vertex fog 1: table fog bit 0 fog enable (fe) texture factor (118) write only address: dp_base + 118h power-on default: undefined bit 31:24 alpha - to be used in pixel blending bit 23:16 red bit 15:8 green bit 7:0 blue fog color (11c) write only address: dp_base + 11ch power-on default: undefined bit 31:24 alpha reference value bit 23:0 rgb fb_zb stride register (120) write only address: dp_base + 120h power-on default: undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 alpha red 1514131211109876543210 green blue 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 process id reserved pce se fbf sm source blending 1514131211109876543210 destination blending abe alpha test reserved ate de tft fe
27 - 12 3d registers silicon motion ? , inc. SM731 confidential databook bit 31:16 frame buffer stride bit 15:0 z buffer stride z base address (124) write only address: dp_base + 124h power-on default: undefined bit 31:0 base address in qdw (128-bit) unit 3d display address (128) write only address: dp_base + 128h power-on default: undefined bit 31:0 3d display address in qdw (128-bit) unit draw buffer base address (12c) write only address: dp_base + 12ch power-on default: undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 frame buffer stride 1514131211109876543210 z buffer stride 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 base address in qdw 1514131211109876543210 base address in qdw 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 3d base display address in qdw 1514131211109876543210 3d base display address in qdw 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 draw buffer base address in qdw 1514131211109876543210 draw buffer base address in qdw
3d registers 27 - 13 silicon motion ? , inc. SM731 confidential databook bit 31:0 draw buffer base address in qdw (128-bit) unit clip top left register (130) write only address: dp_base + 130h power-on default: undefined bit 31:16 clip top register bit 15:0 clip left register clip bottom right register (134) write only address: dp_base + 134h power-on default: undefined bit 31:16 clip bottom register bit 15:0 clip right register window size (138)* write only address: dp_base + 138h power-on default: undefined bit 31:30 reserved bit 29:16 height bit 15:14 reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 clip top register 1514131211109876543210 clip left register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 clip bottom register 1514131211109876543210 clip right register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved height 1514131211109876543210 reserved width
27 - 14 3d registers silicon motion ? , inc. SM731 confidential databook bit 13:0 width zw norm_1 (13c) write only address: dp_base + 13ch power-on default: undefined bit 31:0 32-bit floating point wnear in w buffer (internal use unsigned 24-bit float); zw norm_2 (140) write only address: dp_base + 140h power-on default: undefined bit 31:0 = (2^n - 1)/(wfar - wnear) if w buffer = z scale when in z buffer in floating point note: wnorm = (w - zw_norm_1) * zw_norm_2; to make the better resolution in w buffer fog norm_1 (144) write only address: dp_base + 144h power-on default: undefined bit 31:0 w1 in floating point 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 32-bit floating point wnear in w buffer 1514131211109876543210 32-bit floating point wnear in w buffer 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 zw norm_2 1514131211109876543210 zw norm_2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 w1 in floating point 1514131211109876543210 w1 in floating point
3d registers 27 - 15 silicon motion ? , inc. SM731 confidential databook fog norm_2 (148) write only address: dp_base + 148h power-on default: undefined bit 31:0 = 255/(w2 - w1) note: fog_lut_index = (w - fog_norm_1) * (fog_norm_2); text_bump_env (160 & 1b0) write only address: dp_base + 160h; dp_base + 1b0h power-on default: undefined bit 31:0 reserved text_bump_env_mat (164 & 1b4) write only address: dp_base + 164h; dp_base + 1b4h power-on default: undefined bit 31:24 bumpenvmat11 bit 23:16 bumpenvmat10 bit 15:8 bumpenvmat01 bit 7:0 bumpenvmat00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 fog norm_2 1514131211109876543210 fog norm_2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bumpenvmat11 bumpenvmat10 1514131211109876543210 bumpenvmat01 bumpenvmat00
27 - 16 3d registers silicon motion ? , inc. SM731 confidential databook texture border color (168 & 1b8) write only address: dp_base + 168h; dp_base + 1b8h power-on default: undefined bit 31:24 alpha bit 23:16 red bit 15:8 green bit 7:0 blue texture color key 1 (16c & 1bc) write only address: dp_base + 16c; dp_base + 1bch power-on default: undefined bit 31:24 alpha bit 23:16 red bit 15:8 green bit 7:0 blue texture color key 2 (170 & 1c0) write only address: dp_base + 170h; dp_base + 1c0h power-on default: undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 alpha red 1514131211109876543210 green blue 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 alpha red 1514131211109876543210 green blue 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 alpha red 1514131211109876543210 green blue
3d registers 27 - 17 silicon motion ? , inc. SM731 confidential databook bit 31:24 alpha bit 23:16 red bit 15:8 green bit 7:0 blue texture blending register (174 & 1c4) write only address: dp_base + 174h; dp_base + 1c4h power-on default: undefined bit 31 reserved (r) bit 30:29 argument2 color modifier selection; second set of argument selection (acm) 00 no modify 01 color replicate 10 complement 11 reserved bit 28:26 argument 2 color selection (acs) 000 diffuse color 001 previous stage output 010 texture 011 texture factor from reg 118 100 specular else reserved bit 25:24 argument1 color modifier selection; first set of argument selection (acmf) bit 23:21 argument1 color selection (acs1) bit 20:16 color blend operation 00000 disable 00001 select argument1 00010 select argument2 00011 multiply; arg1 * arg2 00100 multiply 2x; (arg1 * agr2) * 2 00101 multiply 4x; (arg1 * arg2) * 4 00110 add; arg1 + arg2 00111 add signed; arg1 + arg2 - 0.5 01000 add signed 2x (arg1 + arg2 - 0.5) << 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r acm acs acmf acs1 color blend 1514131211109876543210 r ams aas ams1 aas1 alpha blend operation
27 - 18 3d registers silicon motion ? , inc. SM731 confidential databook 01001 subtract; arg1 - arg2 01010 add smooth arg1 + arg2 - arg1*agr2 01011 blend diffuse alpha; arg1*alphad + arg2*(1 - alphad) 01100 blend texture alpha; blend the arguments with texture alpha 01110 blend factor alpha; blend the arguments with factor (morphing) alpha 01111 blend texture pm; arg1 + arg2*(1 - alpha) 10000 pre-modulate; modulate this texture stage with next texture stage 10001 modulate alpha add color; arg1rgb + arg1a * arg2rgb 10010 modulate color add alpha arg1rgb * arg2rgb + arg1a 10011 modulate inverted alpha add color;(1 - arg1a)*arg2rgb + arg1rgb 10100 modulate inverted color add alpha;(1 - arg1rgb)*arg2rgb + arg1a 10101 bump environment map without luminance 10110 bump environment map with luminance 10111 dot product 3; arg1r*arg2r + arg1g*agr2g + arg1b*arg2b bit 15 reserved (r) bit 14:13 argument2 alpha modifier selection (ams) bit 12:10 argument2 alpha selection (aas) bit 9:8 argument1 alpha modifier selection (ams1) bit 7:5 argument1 alpha selection (aas1) bit 4:0 alpha blend operation 00000 disable 00001 select argument1 00010 select argument2 00011 multiply; arg1 * arg2 00100 multiply 2x; (arg1 * agr2) * 2 00101 multiply 4x; (arg1 * arg2) * 4 00110 add; arg1 + arg2 00111 add signed; arg1 + arg2 - 0.5 01000 add signed 2x; (arg1 + arg2 - 0.5) << 1 01001 subtract arg1 - arg2 01010 add smooth arg1 + arg2 - arg1*agr2 01011 blend diffuse alpha; arg1*alphad + arg2*(1 - alphad) 01100 blend texture alpha; blend the arguments with texture alpha 01110 blend factor alpha; blend the arguments with factor (morphing) alpha 01111 blend texture pm; arg1 + arg2*(1 - alpha) 10000 pre-modulate; arg1 a 10001 modulate alpha add color; alpha d 10010 modulate color add alpha alpha d 10011 modulate inverted alpha add color;alpha d 10100 modulate inverted color add alpha;alpha d 10101 reserved 10110 reserved 10111 dot product 3; alpha d
3d registers 27 - 19 silicon motion ? , inc. SM731 confidential databook text0_lod_textid (178) & text1_lod_textid (1c8) write only address: dp_base + 178h; dp_base + 1c8 power-on default: undefined bit 31:26 reserved bit 25:16 lod bias (s + 4.5) bit 15:8 texture id bit 7:4 maximum texture level - start level (base level in opengl) when lod < maximum texture level, lod = maximum texture level. bit 3:0 minimum texture level - clamp level (called max level in opengl) text0_reg (17c) & text1_reg (1cc) write only address: dp_base + 17ch; dp_base + 1cc power-on default: undefined bit 31 color key enable (cke) bit 30 color key blend enable (ckb) bit 29:27 reserved bit 26 mipmap enable (me) bit 25 mipmap filter 0: point - select one map 1: linear - linear between map bit 24:23 minification filter 00: point 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved lod bias (s + 4.5) 1514131211109876543210 texture id maximum texture minimum texture 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 cke ckb reserved me mf min filter mag filter texture color format 1514131211109876543210 size v size u ps amv amu wv wu te
27 - 20 3d registers silicon motion ? , inc. SM731 confidential databook 01: linear 10: anisotropic 11: reserved bit 22:20 magnification filter 000: point 001: linear 010: anisotropic 011 to 111: reserved bit 19:16 texture color format 0000: argb8888 0001: argb4444 0010: argb1555 0011: rgb565 0100: reserved 0101: dxt1 0110: dxt2 0111: dxt3 1000: dxt4 1001: dxt5 else: reserved bit 15:12 size v; 2^v bit 11:8 size u; 2^u bit 7 point sample floor (ps) bit 6:5 address mode v (amv) 00: border color 01: wrap 10: clamp 11: mirror bit 4:3 address mode u (amu) 00: border color 01: wrap 10: clamp 11: mirror bit 2 wrap v (wv) bit 1 wrap u (wu) bit 0 texture0 enable (te)
3d registers 27 - 21 silicon motion ? , inc. SM731 confidential databook text0_texture level 0 base address (180) & text1_texture level 0 base address(1d0) write only address: dp_base + 180h; dp_base + 1d0h power-on default: undefined bit 31 agp/local (agp) 0: local memory 1: agp memory bit 30 flush cache (fc) 0: normal operation 1: invalidate the texture in the cache. note: when set flush cache, it will generate an one clock pulse to flush the cache, and reset this bit back to 0 after the clock pulse. bit 29:25 reserved bit 24:0 base address in unit of 128_byte texture level 1 base address (184 & 1d4) write only address: dp_base + 184h; dp_base + 1d4h power-on default: undefined bit 31 agp/local (agp) 0 = word memory 1 = agp memory bit 30:25 reserved bit 24:0 base address in unit of 128-byte 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 agp fc reserved base address 1514131211109876543210 base address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 agp reserved base address 1514131211109876543210 base address
27 - 22 3d registers silicon motion ? , inc. SM731 confidential databook texture level 2 base address (188 & 1d8) write only address: dp_base + 188h; dp_base + 1d8h power-on default: undefined description same as texture level 1 base address (184 & 1d4) . texture level 3 base address (18c & 1dc) write only address: dp_base + 18ch; dp_base + 1dch power-on default: undefined description same as texture level 1 base address (184 & 1d4) . texture level 4 base address (190 & 1e0) write only address: dp_base + 190h; dp_base + 1e0h power-on default: undefined description same as texture level 1 base address (184 & 1d4) . texture level 5 base address (194 & 1e4) write only address: dp_base + 194h; dp_base + 1e4h power-on default: undefined description same as texture level 1 base address (184 & 1d4) . texture level 6 base address (198 & 1e8) write only address: dp_base + 198h; dp_base + 1e8h power-on default: undefined description same as texture level 1 base address (184 & 1d4) . texture level 7 base address (19c & 1ec) write only address: dp_base + 19ch; dp_base + 1ech power-on default: undefined description same as texture level 1 base address (184 & 1d4) . texture level 8 base address (1a0& 1f0) write only address: dp_base + 1a0h; dp_base + 1f0h power-on default: undefined
3d registers 27 - 23 silicon motion ? , inc. SM731 confidential databook description same as texture level 1 base address (184 & 1d4) . texture level 9 base address (1a4 & 1f4) write only address: dp_base + 1a4h; dp_base + 1f4h power-on default: undefined description same as texture level 1 base address (184 & 1d4) .

2d3d dma register 28 - 1 silicon motion ? , inc. SM731 confidential databook chapter 28: 2d3d dma registers 2d 3d address space arrangement: 000 - 0ff : 2d & dma shadow registers 100 - 3ff : 3d registers 400 - 4ff : vertex 0 registers 500 - 5ff : vertex 1 registers 600 - 6ff : vertex 2 registers 700 - 7ff : global fog registers 256x8 (=64x32) 10000 - 8ffff : dma slave write port addr bit_[31:0] 2d addr bit_[31:0] dma shadow reg comments 0 13+14 xs_k1,ys_k2 80 32 dma start address shared with 3000 4 13+14 xd,yd 84 32 write back address shared with 3004 8 13+14 dimx,dimy_et 88 32 total transfer size shared with 3008 c 16+16 cmd_ctl,rop 8c 32 dma address mask for circular dma buffer 300c addr&!mask | start_addr&mask 10 13+13 d_pitch,s_pitch 90 28 sleep counter loop header activate dma when count reach 0 14 32 fgc 94 32 18 24 bgc 98 32 1c 15+12 ps_xy,stretch_h 9c 32 20 24 compare_color a0 32 agp write back data register write back data_[31:0] read thru 3020 24 24 cc_mask a4 32 " wb data_[63:32] - r3024 28 8+16 bytemask, bitmask a8 32 " wb data_[95:64] - r3028 2c 13+14 clip_t,clip_l ac 32 " wb data_[127:96] - r302c 30 13+13 clip_b,clip_r b0 32 34 32 mono_pattern_low b4 32 38 32 mono_pattrn_high b8 32 3c 13+13 d_xywid,s_xywid bc 32 40 1+24 s_base c0
28 - 2 2d3d dma register silicon motion ? , inc. SM731 confidential databook 44 1+24 d_base c4 48 8 alpha for bitblt c8 4c cc 50 d0 54 d4 58 d8 5c dc 60 e0 64 e4 68 e8 6c ec 70 f0 74 f4 78 f8 fc address bit function comment 3000 31:0 dma start address [27:0] in quad dword unit share with 2d reg_80 3004 31:0 write back address [27:0] in quad dword unit with data at reg_a0 3008 31:0 total transfer size in qdword [21:0]: size in qdword [27:26]: write back req [30:28]: req water mark [31]: activate dma 300c 27:0 dma address mask agp_addr = addr&mask | start_addr&!mask; 3010 31:0 sleep counter read only, write thru 90 301c 31:0 2nd dma agp start address read only, write thru 9c 3020 31:0 write back data [31:0] 3024 31:0 " [63:32] 3028 31:0 " [95:64] 302c 31:0 " [127:96] 3030 31:0 3034 31:0 3038 31:0 addr bit_[31:0] 2d addr bit_[31:0] dma shadow reg comments
2d3d dma register 28 - 3 silicon motion ? , inc. SM731 confidential databook table 33: summary of 2d 3d dma registers 303c 31:0 3040 31:0 3044 31:0 3048 31:0 304c 31:0 3050 31:0 summary of registers page dma start address (3000) 28 - 4 dma write back address (3004) 28 - 4 total transfer size (3008) 28 - 4 write back data (3020 - 302c) 28 - 4 performance monitoring registers (3054 - 3060) - internal use only 28 - 5 device 1 status (3064) - internal use only 28 - 6 dma data header specification generic format 28 - 6 primitive data header (type=0000) 28 - 7 2d3d command pair (type=0001) 28 - 8 texture data (type=0010) 28 - 8 status test register (type=0011) 28 - 9 loading of single register (type=0100) 28 - 9 2d hbltw data (type=0111) 28 - 10 write back header (type=1000) 28 - 10 loop dma activated with sleep counter (type=1110) 28 - 10 dummy header (type=1111) 28 - 10 address bit function comment
28 - 4 2d3d dma register silicon motion ? , inc. SM731 confidential databook dma start address (3000) read/write address: pci_base + 3000h power-on default: undefined bit 31:28 reserved bit 27:0 dma start address in quad double word as a unit dma write back address (3004) read/write address: pci_base + 3004h power-on default: undefined bit 31:28 reserved bit 27:0 dma write back address in quad double word as a unit total transfer size (3008) read/write address: pci_base + 3008h power-on default: undefined bit 31 dma 1 = activate dma 0 = dma idle - after dma complete, this bit will be reset to 0 by hardware bit 30:28 reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved dma start address 1514131211109876543210 dma start address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved dma write back 1514131211109876543210 dma write back 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 dma reserved wb reserved total transfer size in quad dword 1514131211109876543210 total transfer size in quad dword
2d3d dma register 28 - 5 silicon motion ? , inc. SM731 confidential databook bit 27:26 write back (wb) 00 = no write back 01 = reserved 1x = write back 128-bit " bit 25:22 reserved bit 21:0 total transfer size in quad dword. total could transfer 64mb dma data. write back data (3020 - 302c) read only address: power-on default: bit 127:96 write back data (302c) bit 95:64 write back data (3028) bit 63:32 write back data (3024) bit 31:0 write back data (3020) performance monitoring registers (3054 - 3060) - internal use only read only address: pci_base + 3054h...3060h power-on default: undefined control by programming the device0 register. bit 31:18 reserved bit 17 device0: enable the performance count. (epc) bit 16 device0: reset the performance counter (rpc) bit 15:0 reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved epc rpc 1514131211109876543210 reserved write back data (302c) 127 95 64 63 0 96 32 31 write back data (3028) write back data (3024) write back data (3020)
28 - 6 2d3d dma register silicon motion ? , inc. SM731 confidential databook device 1 status (3064) - internal use only read only address: pci_base + 3064h power-on default: undefined control by programming the device0 register. bit 31:4 reserved bit 3 zero cycle map (zcm) 0: zero cycle map test fail or not test 1: zero cycle map sram test pass bit 2 z cache (zc) 0: z cache test fail or not test 1: z cache sram test pass bit 1 pixel cache (pc) 0: pixel cache test fail or not test 1: pixel cache sram test pass bit 0 status bits (sb) 0: status bits 14c_[6:1] invalid 1: status bits 14c_[6:1] valid note: to initiate the internal sram self test by program device0(100)_[12] to 1 bit [3:0] valid only when 100_[12] = 1 dma data header specification generic format qdword size [63:32] - total transfer size in quad dword or 32 register data bit 31:28 dma type 0000: 3d primitive data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 reserved zcm zc pc sb qd word size or single register 32-bit data dma type local memory address 63 32 31 28 27 25 24 0 reserved
2d3d dma register 28 - 7 silicon motion ? , inc. SM731 confidential databook 0001: 2d3d command - consecutive registers with 64-bit header and pairs of dword registers 0010: texture data - host data loading to local memory linearly 0011: device status test command 0100: loading of single register 0101: reserved 0110: reserved 0111: 2d hbltw data 1000: write back header 1110: loop dma with sleep counter dma activation 1111: dummy header - will be trash out at parser else: reserved for future expansion bit 27:25 reserved bit 24:0 local memory address - each unit is 128-bit address space in local memory primitive data header (type=0000) dword count [50:32]: total number of dword count for all vertex registers follow this header bit 25:22 primitive type 4'b0000: primtype_points 4'b0001: primtype_indexedlinelist 4'b0010: primtype_linelist 4'b0011: primtype_linestrip 4'b0100: primtype_indexedlinestrip 4'b0101: primtype_linelist_imm 4'b1000: primtype_trianglelist 4'b1001: primtype_indexedtrianglelist 4'b1010: primtype_indexedtrianglelist2 4'b1011: primtype_trianglestrip 4'b1100: primtype_indexedtrianglestrip 4'b1101: primtype_trianglefan 4'b1110: primtype_indexedtrianglefan 4'b1111: primtype_trianglefan_imm bit 21:19 primitive mode 3'b000: primmode_immediate 3'b001: primmode_vtx_buffer 3'b010: primmode_vtx_indexbuf 3'b011: primmode_index_buf bit 18 fvf reserved - xyz always on reserved primitive fvf primitive count 63 51 31 28 27 26 25 22 0 dword count dma type 0000 reserved primitive mode ty p e 50 32 21 19 18 11 10
28 - 8 2d3d dma register silicon motion ? , inc. SM731 confidential databook bit 17 0 = rhw off(not included in vertex file) 1 = rhw on bit 16 0 diffuse off(not included in vertex file) 1 diffuse on bit 15 0 = specular off(not included in vertex file) 1 = specular on bit 14:11 number of textures (unvn) bit 10:0 primitive count: number of triangles (no function in hardware) 2d3d command pair (type=0001) consecutive registers pair. 64-bit register data followed this header will be loaded into hardware in order of low dword then high dword. dword count does not include header. texture data (type=0010) host data loading to local memory linearly local memory address 22 bits at quad dword as unit, could address up to 64mb. qdword size 19 bits could transfer up to 8mb -1 size in a dma buffer. reserved register address (offset) 63 51 31 28 27 0 dword count dma type 0001 50 32 14 13 reserved reserved local memory address 63 51 31 28 27 0 dword count dma type 0010 50 32 22 21 reserved
2d3d dma register 28 - 9 silicon motion ? , inc. SM731 confidential databook status test register (type=0011) (memory map system control register xxxx for slave mode) dma fifo not empty "1" if dma queue fifo is not empty. dma busy "1" if dma queue is active. 3d engine fifo not empty "1" if 3d engine fifo is not empty. 3d setup engine busy "1" if 3d setup engine is busy. miu fifo not empty "1" if 2d engine fifo is not empty. 2d engine busy "1" if 2d engine is busy. whenever parsing logic works on status test command, it will stay in hardware test loop if any of the test bit is1 and the corresponding hardware status also true. this is a hardware status waiting for synchronization control.  miu fifo not empty: all 2d, and 3d local memory interface through this fifo.  parser out pipe not empty: true whenever valid register data or valid direct 64 bit data is true.  dma sram fifo empty: this fifo share for slave and mast er mode. and the parser is execute at output of this fifo. so this bit should not be checked at dma fifo. it was design for slave mode status polling. loading of single register (type=0100) for both 2d & 3d registers. only support load 32-bit (2 16-bit 2d registers pair). no single 16-bit register loading. register address (offset) at dword address unit. reserved 63 32 26 dma type 0011 reserved 31 28 27 25 11 9 8 7 2d3d dma 12 reserved reserved active dma sram fifo full dma sram fifo empty 3d setup engine busy 10 64 210 3d z engine 5 3d texture busy parser out pipe not empty miu fifo not empty 2d engine busy 3 3d rasterizer busy 3d pixel engine busy engine busy 32-bit register data register address (offset) 63 31 28 27 0 dma type 0100 32 14 13 reserved
28 - 10 2d3d dma register silicon motion ? , inc. SM731 confidential databook 2d hbltw data (type=0111) tie with 2d engine follow the header is hbltw data. before execute this header, 2d hbltw registers should be setup - insert the 2d command before this header. write back header (type=1000) when the dma parser executes this header, it will generate a write back master request to the agp address (specified at register 3004) with a 128-bit data (specified at registers 3020 - 302c). loop dma activated with sleep counter (type=1110) when hardware parser detects this header, it will trash all the data in the dma fifo and reset the dma to timed sleep mode dummy header (type=1111) use this 64-bit dummy header to make the total dma file size to become an integer number of 128-bits (quad double world). 32-bit register data 63 31 28 27 0 dma type 0111 32 reserved reserved 63 31 28 27 0 dma type 1000 32 reserved dma start address in 63 31 28 27 26 25 0 dma type 1110 reserved 32 dma transfer size in qdword qdword unit reserved 63 31 28 27 0 dma type 1111 32 reserved
electrical specifications 29 - 1 silicon motion ? , inc. SM731 confidential databook chapter 29: electrical specifications absolute maximum ratings dc specifications table 34: absolute maximum ratings specification maximum rating ambient temperature (ta) 0 c to 75 c storage temperature -40 c to 125 c voltage on i/o pins with respect to vss - 0.5v to vdd + 5% operating power dissipation tbd core dc power supply voltage 2.5v 5% table 35: digital dc specification name parameter min max unit notes v il input low voltage - 0.8 v v ih input high voltage 2.0 - v v ol output low voltage - 0.4 v v oh output high voltage 2.4 vdd+0.5 v i ozl output tri-state current - 10 a i ozh output tri-state current - 10 a i ozl (pull up pins) output tri-state current -130 -10 a i ozh (pull up pins) output tri-state current - 10 a i ozl (pull down pins) output tri-state current - 10 a i ozh (pull down pins) output tri-state current 10 130 a c in input capacitance tbd pf c out output capacitance tbd pf i cc power supply current tbd ma
29 - 2 electrical specifications silicon motion ? , inc. SM731 confidential databook table 36: ramdac characteristics table 37: ramdac/clock synthesizer dc specifications ac specifications notes: 1. measured from the 50% of vclk to th e 50% point of full scale transaction 2. measured from 10% to 90% full scale 3. with dac outputs equally loaded notes:  condition for v out is a 50 ohm terminated load, use of the internal vref and rfsc = 1.2 k ohms. parameter min typical max unit resolution each dac - 8bits lsb size - 54.7 a output full scale current - 14.0 ma integral linearity error 0 - 1lsb differential linearity error 0 -1lsb dac to dac mismatch 0 -5% power supply rejection ratio 0 - 0.5 % /% avdd output compliance 0 -1.2v output capacitance - -10pf glitch energy - 30 - pv-sec symbol parameter min typical max unit avdd dac supply voltage 3.17 3.3 3.47 v cvdd pll supply voltage 3.17 3.3 3.47 v vref internal dac voltage reference 1.1 1.235 1.35 v table 38: ramdac ac specifications parameter typical max unit notes dac output delay 3 ns 1 dac output rise/fall time 3 ns 2 dac output setting time 15 ns dac-to-dac output skew 2 15 ns 3 parameter i out (ma) v out (v) blank input data white 14.0 0.7 1 ffh data data data 1 data black 0 0 1 00h ~blank 000don't care
electrical specifications 29 - 3 silicon motion ? , inc. SM731 confidential databook ac timing specifications power on reset table 39: power-on reset and configuration reset timing figure 26: power-on reset and reset configuration timing symbol parameter min max unit t1 reset active from vcc stable 5 - ms t2 reset active from external oscillator stable 0 - t3 reset active from ~pwrdn signal stable 2 - ms t4 internal power on ~reset from vcc stable - 200 ns t5 external ~reset to internal power on ~reset inactive - 20 ms t6 external ~reset pulse width - ns t7 configuration cycle setup time 20 - ns t8 configuration cycle hold time 5 vcc 14.318 mhz ~pwrdn t1 t3 stable t7 t8 md[7:0] hi-z t4 t5 t6 internal power on ~reset external ~reset t2
29 - 4 electrical specifications silicon motion ? , inc. SM731 confidential databook figure 27: lvds transmitter device transition times table 40: switching characteristics table 41: lvds specifications note: lvds transmitter licensed from thine electronics, inc. symbol parameter min typ max units t lv t lvds transition time 0.6 1.5 ns symbol parameter conditions min typ max units lvds (cmos/ttl) dc specifications v ih high level input voltage 2.0 vcc v v il low level input voltage gnd 0.8 v i in input current ov v in vcc 10 a lvds driver dc specifications v od differential output voltage rl = 100 ? 250 350 450 mv ? v od change in vod between complimentary output states 35 mv v oc common mode voltage 1.125 1.25 1.375 v ? v oc change in voc between complimentary output states 35 mv i os output short circuit current v out = ov, rl = 100 ? -24 ma i oz output tri-state current /pdwn = 0v, v out = 0v to vcc 80% 80% 20% 20% vdiff t lvt t lvt 100 ? lvds output vdiff = (ta+) - (ta-) ta+ ta- lvds output load
electrical specifications 29 - 5 silicon motion ? , inc. SM731 confidential databook panel on/off sequence figure 28: panel power on figure 29: panel power off fpvdden controls/ data vbiasen fpen 0 - t t t t is programmed via fpr33 [3:2] fpvdden controls/ data vbiasen fpen t t 0 - t t is programmed via fpr33 [3:2]
29 - 6 electrical specifications silicon motion ? , inc. SM731 confidential databook pci bus cycles table 42: pci bus timing (33 mhz) figure 30: pci bus timing diagram symbol parameter min max unit t1 ~frame setup to clk 7 - ns t2 ad[31:0] (address) setup to clk 7 - ns t3 ad[31:0] (address) hold from clk 0 - ns t4 ad[31:0] (read data) valid from clk 2 11 ns t5 ad[31:0] (read data) hold from clk 0 - ns t6 ad[31:0] (write data) setup to clk 7 - ns t7 ad[31:0] (write data) hold from clk 0 - ns t8 c/~be[3:0] (command) setup to clk 7 - ns t9 c/~be[3:0] (command) hold from clk 0 - ns t10 c/~be[3:0] (byte enable) hold from clk 0 - ns t11 ~trdy high-z to high from clk 2 - ns t12 ~trdy active from clk 2 11 ns t13 ~trdy inactive from clk 2 11 ns t14 ~trdy high before high-z 1t - clk t15 ~irdy setup to clk 7 - ns t16 ~irdy hold from clk 0 - ns t17 ~devsel active from clk 2 11 ns t18 ~devsel inactive from clk 2 11 ns t19 ~devsel high before high-z 1t - clk ~frame read ad[31:0] c/~be[3:0] ~irdy ~trdy ~devsel write ad[31:0] byte enables byte enables address command read data t1 address write data t2 t3 t4 t5 t6 t7 t8 t9 t17 write data t18 t15 t16 t12 t13 1 2 3 4 5 6 t11 t14 t19 t2 t3 t10 turn-around cycle hi-z state
electrical specifications 29 - 7 silicon motion ? , inc. SM731 confidential databook agp bus cycles table 43: agp 1x mode bus timing figure 31: agp bus timing diagram table 44: agp 2x timing parameters symbol parameter min spec max spec units t cyc clk cycle time 15.0 30.0 ns t valc clk to control signal (output) valid delay 1.0 5.5 ns t vald clk to data (output) valid delay 1.0 6.0 ns t on float to active (output) delay 1.0 6.0 ns t off active to float (output) delay 1.0 14.0 ns t suc control signals (input) setup time to clk 6.0 - ns t sud data (input) setup time to clk 5.5 - ns t h control signals (input) hold time to clk 0.0 - ns symbol description min (ns) max (ns) tclk clock - 15 tdvb data valid before strobe 1.7 tdva data valid after strobe 1.9 tval clk to control signal and data valid delay 1 5.5 th control signals hold time to clk 0 - 66 mhz clk data t cyc t vald t valc control t sud t suc t h t off t on
29 - 8 electrical specifications silicon motion ? , inc. SM731 confidential databook figure 32: agp 2x read request with return data (4qw) table 45: agp4x timing parameters symbol description min (ns) max (ns) tclk clock - 15 tdvb data valid before strobe tbd tdva data valid after strobe tbd tval clk to control signal and data valid delay 1 5.5 th control signals hold time to clk 0 - request 1 idle irdy# request 2 request 3 idle ad d0 d1 d2 d3 d4 d5 d6 d7 trdy# st(2:0) 000 gnt# sba(7:0) a3l1 a3l0 a1h1 a1h0 a1m1 a1m0 a1l1 a1l0 a2l1 a2l0 ff ff clk ad_stbx sb_stb tclk th tval
electrical specifications 29 - 9 silicon motion ? , inc. SM731 confidential databook synchronous dram (sdram) and sgram cycles table 46: sdram/sgram memory read timing note: t = sdck clock period figure 33: sdram/sgram read and write cycles symbol parameter min max unit t1 sdck cycle time 12 ns t2 sdck high time 4 ns t3 sdck low time 4 ns t4 sdcken hold time 3.5 ns t5 sdcken setup time 3.5 ns t6 command ( ~ cs, ~ ras, ~ cas, ~ we, dsf, dqm) setup time 3.5 ns t7 command ( ~ cs, ~ ras, ~ cas, ~ we, dsf, dqm) hold time 3.5 ns t8 address/ba setup time 3.5 ns t9 address/ba hold time 2.5 ns t10 access time from sdck t-2 ns t11 data out hold time from sdck 4 ns t12 data in setup time from sdck 3.5 ns t13 data in hold time from sdck 3.5 ns t14 active to read, write delay 3t t15 read latency 3t t16 write recovery time 2t sdck sdcken ~cs ~ras ~cas a0-a7 a8 ba ~we dsf dqm dq rb rb cb0 bank bank qa0 qa1 db0 db1 qa2 qa3 db2 db3 t1 t2 t3 t4 t5 t6 t7 t6 t7 t6 t7 t8 t9 ra t8 t9 ca0 t8 t9 t8 t9 ra bank t8 t9 bank t14 t15 t10 t11 t12 t13 row active (a-bank) read (a-bank) precharge (a-bank) precharge (b-bank) row active (b-bank) write (b-bank) t16
29 - 10 electrical specifications silicon motion ? , inc. SM731 confidential databook flat panel interface cycle timing table 47: color tft interface timing note: t = pixel clock rate on lcd figure 34: tft interface timing symbol parameter min max unit t1 tft fpsclk cycle time 12 ns t2f fdata setup to fpsclk falling edge 0.5t-2 ns t3f fdata hold from fpsclk falling edge 0.5t-2 ns t4f de setup to fpsclk falling edge 0.5t-4 ns t5f de hold from fpsclk falling edge 0.5t-4 ns t2r fdata setup to fpsclk rising edge 0.5t-2 ns t3r fdata hold from fpsclk rising edge 0.5t-2 ns t4r de vsync setup to fpsclk rising edge 0.5t-4 ns t5r de vsync hold from fpsclk rising edge 0.5t-4 ns t6 fhsync pulse width 8 16 t t7 fvsync pulse width 1 fhsync data fpsclk fdata t1 t2 f t3 f t2 r t3 r de t4 f t5 f t4 r t5 r fhsync t6 fvsync t7
mechanical dimensions 30 - 1 silicon motion ? , inc. SM731 confidential databook chapter 30: mechanical dimensions figure 35: 385 bga mechanical dimensions d d2 e2 e detail b 0.10 0.30 ? ? c s c s ab 3 ?b 0.984 1.100 bsc 1.142 1.142 1.220 0.984 1.220 30 typ 0.050 basic 0.022 1.100 bsc 0.046 0.030 0.024 0.092 dimension in inch 1.134 29.00 29.20 28.80 e2 o e3 e ddd 0.20 30 typ 25.00 1.27 basic 28.80 1.12 0.50 30.80 0.51 30.80 0.60 2.13 min d d3 e e1 d1 d2 a2 c b a a1 1.213 31.00 31.20 29.20 31.20 25.00 27.94 bsc 31.00 27.94 bsc 29.00 1.213 1.134 1.22 0.70 0.61 0.90 2.53 max 1.17 0.56 0.75 0.60 2.33 nom 0.044 0.020 0.024 0.020 0.084 min nom dimension in mm symbol 1.150 0.008 1.228 1.228 1.150 0.048 0.024 0.035 0.028 0.100 max 17 15 13 11 9 7 5 3 1 8 6 4 2 16 14 12 10 t u a b c d e f g h j k l m n p r e d1 e1 b -a- -b- 18 20 22 19 21 23 v w y aa ab ac a' a2 o a1 -c- 2 a detail a' c c ddd between the edge of the solder ball and the 5. reference document : jedec mo-151, ban-2 4. there shall be a minimum clearance of 0.25 mm body edge. 3. dimension b is measured at the maximum solder ball diameter, parallel to primary datum c. 2. primary datum c and seating plane are defined by the spherical crowns of the solder balls. 1. controlling dimension: millimeter. note:

video modes a - 1 silicon motion ? , inc. SM731 confidential databook appendix a: video modes this appendix lists the various tables of video modes supported under various configurations of SM731: crt only, lcd only, or simultaneous. the parameters listed in the following tables define the standard capabilities of the SM731 when it is used with the silicon motion's video bios. abbreviations used: txt: text mode gr: graphics mode standard ibm compatible vga modes the table details the standard vga modes supported in crt only. table 48: standard ibm compatible vga modes note: for modes 3 and 7, 8-dot fonts are used on the lcd. mode # (hex) type colors alpha resolution font clock mhz hsync khz vsync hz memory min buffer start 0,1 txt 16 40x25 320x200 8x8 25.175 31.55 70.3 256k b8000 0,1* txt 16 40x25 320x350 8x14 25.175 31.55 70.3 256k b8000 0,1+ txt 16 40x25 360x400 9x16 28.322 31.34 69.8 256k b8000 2,3 txt 16 80x25 640x200 8x8 25.175 31.55 70.3 256k b8000 2,3* txt 16 80x25 640x350 8x14 25.175 31.55 70.3 256k b8000 2,3+ txt 16 80x25 720x400 9x16 28.322 31.34 69.8 256k b8000 4,5 gr 4 40x25 320x200 8x8 25.175 31.55 70.3 256k b8000 6 gr 2 80x25 640x200 8x8 25.175 31.55 70.3 256k b8000 7 txt mono 80x25 720x350 9x14 28.322 31.34 69.8 256k b8000 7+ txt mono 80x25 720x400 9x16 28.322 31.34 69.8 256k b8000 d gr 16 40x25 320x200 8x8 25.175 31.55 70.3 256k a0000 e gr 16 80x25 640x200 8x8 25.175 31.55 70.3 256k a0000 f gr mono 80x25 640x350 8x14 25.175 31.55 70.3 256k a0000 10 gr 16 80x25 640x350 8x14 25.175 31.55 70.3 256k a0000 11 gr 2 80x30 640x480 8x16 25.175 31.55 60.1 256k a0000 12 gr 16 80x30 640x480 8x16 25.175 31.55 60.1 256k a0000 13 gr 256 40x25 320x200 8x8 25.175 31.55 70.3 256k a0000
a - 2 video modes silicon motion ? , inc. SM731 confidential databook vesa super vga modes vesa extended video modes are supported by the lynx family bios (subject to the constraints of the video subsystem hardware) as follows: table 49: vesa super vga modes low resolution modes the bios supports low-resolution modes from 320x200 to 640x400 in 8/16-bit colors for directdraw. the low resolution modes are defined as follows: table 50: low resolution modes note: for modes 320x240 and 400x300, default refresh rate is set to 60hz and optimal is set to 75hz. vesa mode # (hex) extended mode type colors alpha resolution font memory min buffer start (min.) buffer start 101 50 gr 256 80x30 640x480 8x16 512k a0000 102 6a gr 16 100x75 800x600 8x8 256k a0000 103 55 gr 256 100x75 800x600 8x8 512k a0000 104 6b gr 16 128x48 1024x768 8x16 512k a0000 105 60 gr 256 128x48 1024x768 8x16 1m a0000 107 65 gr 256 160x64 1280x1024 8x16 2m a0000 111 52 gr 64k 80x30 640x480 8x16 1m a0000 112 53 gr 16m 80x30 640x480 8x16 1m a0000 114 57 gr 64k 100x75 800x600 8x8 1m a0000 115 58 gr 16m 100x75 800x600 8x8 2m a0000 117 62 gr 64k 128x100 1024x768 8x8 2m a0000 118 63 gr 16m 128x100 1024x768 8x8 4m a0000 11a 67 gr 64k 160x128 1280x1024 8x8 4m a0000 11b 68 gr 16m 160x128 1280x1024 8x8 4m a0000 mode # (hex) type colors resolutions vsync (hz) video memory buffer start 40 gr 256 320x200 70 1mb a0000 41 gr 64k 320x200 70 1mb a0000 42 gr 256 320x240 75, 60 1mb a0000 43 gr 64k 320x240 75, 60 1mb a0000 44 gr 256 400x300 75, 60 1mb a0000 45 46 gr gr 64k 256 400x300 75, 60 1mb a0000 512x384 75 1mb a0000 47 gr 64k 512x384 75 1mb a0000 48 gr 256 640x400 70 1mb a0000 49 gr 64k 640x400 70 1mb a0000
video modes a - 3 silicon motion ? , inc. SM731 confidential databook 640 by 480 resolution modes table 51: 640 x 480 extended modes note: for the above resolutions, the default refresh rate for lcd and simul mode is 60hz. 800 by 600 resolution modes table 52: 800x600 extended modes note: for the above resolutions, the default refresh rate for lcd and simul mode is 60hz. mode # (hex) vesa mode # (hex) type colors alpha format font vclk (mhz) hsync +/- (khz) vsync +/- (hz) video memory buffer start 50 101 gr 256 80x30 8x16 25.175 31.5 60.0 512 kb a0000 31.5 37.5- 75.0- 36 43.3 85.0 52 111 gr 64k 80x30 8x16 25.0 31.5 60.0 1mb a0000 31.5 37.5- 75.0- 36 43.3 85.0 53 112 gr 16m (24-bit) 80x30 8x16 25.0 31.5 60.0 1mb a0000 31.5 37.5- 75.0- 36 43.3 85.0 54 gr 16m (32-bit) 80x30 8x16 25.0 31.5 60.0 2mb a0000 31.5 37.5- 75.0- 36 43.3 85.0 mode # (hex) vesa mode# (hex) type colors alpha format font vclk (mhz) hsync +/- (khz) vsync +/- (hz) video memory buffer start 6a 6a gr 16 100x75 8x8 40.0 37.9+ 60.3+ 256kb a0000 55 103 gr 256 100x75 8x8 40.0 37.9+ 60.3+ 512kb a0000 49.5 46.9+ 75.0+ 56.25 53.7 85.0 57 114 gr 64k 100x75 8x8 40.0 37.9+ 60.3+ 1mb a0000 49.5 46.9+ 75.0+ 56.25 53.7 85.0 58 115 gr 16m (24-bit) 100x75 8x8 40.0 37.9+ 60.3+ 2mb a0000 49.5 46.9+ 75.0+ 56.25 53.7 85.0 59 gr 16m (32-bit) 100x75 8x8 40.0 37.9+ 60.3+ 2mb a0000 49.5 46.9+ 75.0+ 56.25 53.7 85.0
a - 4 video modes silicon motion ? , inc. SM731 confidential databook 1024 by 768 resolution modes table 53: 1024x768 extended modes note: for the above resolutions, the default refresh rate for lcd and simul mode is 60hz 1280 by 1024 resolution modes table 54: 1280x1024 extended modes note: for the above resolutions, the default refresh rate for lcd and simul mode is 60hz mode # (hex) vesa mode# (hex) type colors alpha format font vclk (mhz) hsync +/- (khz) vsync +/- (hz) video memory buffer start 6b 104 gr 16 128x48 8x16 65.0 48.4 - 60.0 - 512kb a0000 60 105 gr 256 128x48 8x16 65.0 48.4 - 60.0 - 1mb a0000 78.8 60.0+ 75.0+ 94.5 68.7 85.0 62 117 gr 64k 128x48 8x16 65.0 48.4 - 60.0 - 2mb a0000 78.8 60.0+ 75.0+ 94.5 68.7 85.0 63 118 gr 16m (24-bit) 128x48 8x16 65.0 48.4 - 60.0 - 4mb a0000 78.8 60.0+ 75.0+ 94.5 68.7 85.0 64 gr 16m (32-bit) 128x48 8x16 65.0 48.4 - 60.0 - 4mb a0000 78.8 60.0+ 75.0+ 94.5 68.7 85.0 mode # (hex) vesa mode# (hex) type colors alpha format font vclk (mhz) hsync +/- (khz) vsync +/- (hz) video memory buffer start 65 107 gr 256 160x64 8x16 78.8 46.4 86.8i+ 2 mb a0000 108 64 60.0 135 79.98 75.0 67 11a gr 64k 160x64 8x16 78.8 46.4 86.8i+ 4 mb a0000 108 64 60.0 135 79.98 75.0 68 gr 16m (24-bit) 160x64 8x16 78.8 46.4 86.8i+ 4 mb a0000 108 64 60.0 135 79.98 75.0
video modes a - 5 silicon motion ? , inc. SM731 confidential databook 1600 by 1200 resolution modes table 55: 1600x1200 extended modes mode # (hex) vesa mode# (hex) type colors alpha format font vclk (mhz) hsync +/- (khz) vsync +/- (hz) video memory buffer start 70 gr 256 200x75 8x16 162 74.5 60 2 mb a0000 202 84 75 229 91.8 85 72 gr 64k 200x75 8x16 112 74.5 60 4 mb a0000 202 84 75 229 91.8 85

popup icon consideration b - 1 silicon motion ? , inc. SM731 confidential databook appendix b: popup icon consideration introduction the silicon supports both the hardware cursor and popup icon. system bios uses the popup icon to display system information, such as: battery status, lcd brightness and more. the display driver for gui operating system uses the hardware cursor to increase performance. since both popup icon and hardware cursor image locations are closely coupled both will be described. this appendix details popup icon support and how to implement the support in system bios. popup icon the popup icons are driven by the lcd and crt backends. the popup icon size is 64x64, and can be zoomed up by 2 to become 128x128 popup icon. the popup icon can be programmed to anywhere on the screen display. for example, in simultaneous mode or extended mode (crt only), a display image is processed through the lcd pipe and the popup icon can be processed though the lcd backend. however, in dual monitor mode (windows 98), the popup icons will be enabled in order to display on the crt and lcd screens. icon pattern memory location the icon pattern memory locations are specified in the foll owing registers: phr80 and phr81 for crt, and fprt160 for lcd. each of these two icon registers allocates 2kb of fscreen video memory within the maximum physical memory. silicon motion assigns the highest 2kb addresses for the physical memory to be installed. the lower 1kb is used to store the popup icon image, and the upper 1kb is used to store the hardware cursor image. figure 36: hardware cursor and popup icon memory location icon pattern each pixel of the icon pattern uses 2-bit to select the di fferent color formats. the table below lists the various color selects: transparent, icon color1 is defined in pop84 register for crt and fprt164 for lcd. memory location 0 lcd popup icon pattern lcd hardware cursor pattern crt popup icon pattern crt hardware cursor pattern
b - 2 popup icon consideration silicon motion ? , inc. SM731 confidential databook furthermore, pixel data is stored in sequential order. for example, bit[7:6] of a byte in the video memory is the first pixel of the icon pattern. bit[5:4] is the second pixel of the icon pattern. each of the popup icon color registers is defined in the same way described below: the 8-bit color register is defined to be 3:3:2 for r:g:b respectively as shown on the table below: the silicon will take the 8-bit icon color and convert it into 24-bit icon color internally. for example, r2r1r0g2g1g0b1b0 will be expanded to r2r1r0r0r0r0r0r0g2g1g0g0g0g0g0g0b1b0b0b0b0b0b0b0. icon control on crt backend register pop82 controls the popup icon enable and size. pop82[7] controls the popup icon enable 0 = disable 1 = enable pop82[6] controls the popup icon size 0 = 64x64 1 = 128x128 icon control on lcd backend register fprt160 controls the popup icon enable and size. fprt160[13] controls the popup icon enable 0 = disable 1 = enable fprt160[12] controls the popup icon size 0 = 64x64 1 = 128x128 icon pattern [1:0] color source 00 transparent 01 icon color1 10 icon color 2 11 icon color 3 bit 7:6 bit 5:4 bit 3:2 bit 1:0 1st pixel 2nd pixel 3rd pixel 4th pixel 76543210 red 2 1 0 green 2 1 0 blue 1 0
popup icon consideration b - 3 silicon motion ? , inc. SM731 confidential databook video bios function call video bios has call services for the popup icon. the table below lists the available video bios function calls. popup icon control (ax = 5f01, bl = 00 - 05) enable/disable popup icon description: this function changes the current status of the popup icon input: ax 5f01h = bl 00h = bh [0] = 0 - no change = = 1 - change crt to icon state [1] = 0 - no change = 1 - change panel icon state [2] = 0 - set to off state = 1 - set to on state output: ax return status = select the size of popup icon description: this function changes the current status of the popup icon input: ax 5f01h = bl 01h = bh [0] = 0 - no change = = 1 - change crt to icon state [1] = 0 - no change = 1 - change panel icon state [2] = 0 - 64x64x2 = 1 - 128x128x2 output: ax return status = set popup icon location description: this function sets the location of the popup icon input: ax 5f01h = bl 02h = bh [0] = 0 - no change
b - 4 popup icon consideration silicon motion ? , inc. SM731 confidential databook = = 1 - change crt to icon state [1] = 0 - no change = 1 - change panel icon state cx x position of the icon = dx y position of the icon = output: ax return status = set popup icon foreground color description: this function sets the foreground color of the popup icon input: ax 5f01h = bl 03h = bh [0] = 0 - no change = = 1 - change crt to icon state [1] = 0 - no change = 1 - change panel icon state ch 1 color index 1 = 2 color index 2 3 color index 3 cl color value for popup icon = output: ax return status = set popup icon background color description: this function loads the background color for the popup icon input: ax 5f01h = bl 04h = bh [0] = 0 - no change = = 1 - change crt to icon state [1] = 0 - no change = 1 - change panel icon state cl background color = dx y position of the icon =
popup icon consideration b - 5 silicon motion ? , inc. SM731 confidential databook output: ax return status = set popup icon bitmap description: this function loads the background bitmap for the popup icon input: ax 5f01h = bl 05h = bh [0] = 0 - no change = = 1 - change crt to icon state [1] = 0 - no change = 1 - change panel icon state es segment of popup icons bitmap = di offset of popup icons bitmap = output: ax return status =

smi handler programming consideration c - 1 silicon motion ? , inc. SM731 confidential databook appendix c: smi handler programming consideration introduction the silicon is designed for notebook systems. notebook systems require support of smm (system management mode) for handling system-wide functions, such as: power management, system hardware control, and proprietary oem-design code. this application note describes consideration fo r system bios when implementing smi (system management interrupt) handler for the silicon. background smm is a special-purpose operating mode provided for hand ling system-wide functions. the main benefit of smm is that it offers an easily isolated processor environment that operates transparently to the operating system or software applications. when smm is invoked through smi, the processor saves the cu rrent state of the processor, then switches to a separate operating environment containe d in the system management ram. while in smm, the processor executes a smi handler code to perform operations such as power down hd when it is idle or displaying an oem-design message on the screen. when the smi handler has completed its operations, it executes a resume instruction. this instruction causes the processor to reload the saved context of the processor, switc h back to protected or real mode, and resume executing the interrupted operating-system program or interrupted application programs. system bios consideration the video bios provides an alternate int 10h entry to al low smi handlers to execute vga bios function calls. this entry point bypasses the sti (set interrupt flag) instruction at the beginning of the standard interrupt handler. int10 vector entry the standard interrupt handler int10 vector is located in 0000:0040h. this int10 handler will issue sti instruction. alternate int10 entry the alternate int10 entry is specified within the content of location c000:0034h. this alternate int10 handler entry does not issue sti. note: for system bios from phoenix, there is a function na med: pmmodifyint10vector that can be used to modify the int10 vector. video bios service calls read/modify the i/o and memory-m apped registers. the memory-mapped registers are accessed through a000-b000 range in real mode or smm; they are video processor registers, drawing engine registers and capture port registers. due to the fact that a000-b000 range is reserved for power management under smm mode, special consideration is necessary: there are two methods as listed below:
c - 2 smi handler programming consideration silicon motion ? , inc. SM731 confidential databook 1. exit smm exit smm when calling video bios services or accessing memory-mapped registers. upon completion, it is ok to resume back to smm. 2. map power management data to another location the default area for storing the power management data is a000-b000. in order to allow video bios services to access a000-b000 area, system bios can map the a000-b000 data to another location, such as d000-e000.
programming usr [3:0] pins d - 1 silicon motion ? , inc. SM731 confidential databook appendix d: programming usr [3:0] pins application notes for control of usr [3:0] pins *gpr 72 is general purpose register 72 with address 3c5h and index 72h gpr 73 is general purpose register 73 with address 3c5h and index 73h usr0 * when usr0 is in input state, the in put status can be read from grp72[2]. usr1 * when usr1 is in input state, the in put status can be read from grp72[3]. usr2 * when usr2 is in input state, the input status can be read from grp73[2]. when toggling usr2 as an input pin, it will generate a hardware interrupt. the status of the in terrupt can be read at bit 2 of scr1c register. gpr72 [4] gpr72 [0] usr0 pad remark 00input* 01input 1 0 output 0 11input gpr72 [5] gpr72 [1] usr1 pad remark 00input* 01input 1 0 output 0 11input gpr73 [5] gpr73 [1] usr1 pad remark 00input* 01input 1 0 output 0 11input
d - 2 programming usr [3:0] pins silicon motion ? , inc. SM731 confidential databook usr3 * when usr3 is in input state, the input status can be read from grp73[3]. when toggling usr3 as an input pin, it will generate a hardware interrupt. the status of the in terrupt can be read at bit 3 of scr1c register. gpr73 [5] gpr73 [1] usr1 pad remark 00input* 01input 1 0 output 0 11input
monitor and tv detect e - 1 silicon motion ? , inc. SM731 confidential databook appendix e: monitor and tv detect crt monitor detect to simplify the monitor detect procedure SM731 implemente d four new registers (ccr7a, ccr7b, ccr7c, ccr7d) and detect circuitry. as for r, g, b corresponds to ccr7a, ccr7b, ccr7c data and ccr7d_[7] as enable. when all these registers are programmed properly, and without waiting for sync period the user s can read back the register 3c2_[4] to determine if the monitor is connected. 3c2_[4] = 0; no monitor detect 3c2_[4] = 1; color monitor detect tv detect to simplify the tv monitor detect procedure SM731 also us es registers (ccr7a, ccr7b, ccr7c, ccr7d), and tv monitor detect circuitry. for y = {ccr7a,00} as 10 bit data for c = {ccr7b,00} as 10 bit data for cvbs = {ccr7c,00} as 10 bit data with ccr7d_[7] as enable and all these registers are programmed properly the users can read back the register ccr7d_[6] to determine svhs monitor's status. ccr7d_[6] = 0; no tv monitor detect ccr7d_[6] = 1; tv monitor detect with ccr7d_[7] as enable and all these registers are programmed properly the users can read back the register ccr7d_[5] to determine cvbs monitor's status. ccr7d_[5] = 0; no tv monitor detect ccr7d_[5] = 1; tv monitor detect

crt and lcd timing register summary f - 1 silicon motion ? , inc. SM731 confidential databook appendix f: crt and lcd timing register summary crt timing register summary table 56: crt timing register summary note: bits shown in bold text are smi extended registers parameter crt register bits [10] [9] [8] [7] [6] [5] [4:0] h total crt00[7] crt00[6] crt00[5] crt00[4:0] h total shadow svr40[7] svr40[6] svr40[5] svr40[4:0] h display end crt01[7] crt01[6] crt01[5] crt01[4:0] h blank start crt02[7] crt02[6] crt02[5] crt02[4:0] h blank start shadow svr41[7] svr41[6] svr41[5] svr41[4:0] h blank end crt33[6] crt33[5] crt05[7] crt03[4:0] h blank end shadow svr44[7] svr42[4:0] h sync start crt04[7] crt04[6] crt04[5] crt04[4:0] h sync start shadow svr43[7] svr43[6] svr43[5] svr43[4:0] h sync end crt05[4:0] h sync end shadow svr44[4:0] v total crt30[3] crt07[5] crt07[0] crt06[7] crt06[6] crt06[5] crt06[4:0] v total shadow svr4a[5] svr4a[0] svr 45[7] svr45[6] svr45[5] svr45[4:0] v sync start crt30[0] crt07[7] crt07[2] crt10[7] crt10[6] crt10[5] crt010[4:0] v sync start shadow svr4a[7] svr4a[2] svr48[7] svr48[6] svr48[5] svr48[4:0] v sync end crt011[3:0] v sync end shadow svr49[3:0] v display end crt30[2] crt07[6] crt07[1] crt12[7] crt12[6] crt12[5] crt012[4:0] v blank start crt30[1] crt09[5] crt07[3] crt15[7] crt15[6] crt15[5] crt015[4:0] v blank start shadow svr4b[5] svr4a[3] svr46[7] svr46[6] svr46[5] svr46[4:0] v blank end crt33[4] crt33[3] crt16[7] crt16[6] crt16[5] crt016[4:0] v blank end shadow svr47[7] svr47[6] svr47[5] svr47[4:0] line compare crt18[7] crt18[6] crt18[5] crt018[4:0] offset crt13[7] crt13[6] crt13[5] crt013[4:0]

index i - 1 silicon motion ? , inc. SM731 confidential databook index numerics 4fsc 15-1 a agc 15-4 agp 29-7 b blue 4-6 c capture 24-2 ccir 601 15-1 clock synthesizer 29-2 closed captioning 15-1, 15-4 color keys 21-6, 22-5 composite video 15-1 crtc 19-9 d device id 3-1 dpms 20-26 drawing engine 20-6, 23-3 g green 4-6 h hardware cursor 20-36, 20-41 horizontal blank 19-10 horizontal sync 19-11 i interlace 20-43 m macrovision 15-1, 15-3 mask 23-15 mclk 20-21, 20-26 mechanical 30-1 memory 19-8 memory clock 4-5 motion comp 25-3 motion compensation 13-1 mpeg-2 13-1 n ntsc 15-1, 15-4 p pal 15-1, 15-4 parity 4-4 pci 18-2, 29-6 pop-up icon 20-37 power down 4-5, 18-8, 20-14 pull-up/ pull-down 4-4 r ramdac 19-31, 29-2 red 4-6 reset 19-6, 29-3 s sdram/sgram 29-9 sequencer 19-6 signature analyzer 21-18, 22-19 sm821 pin diagram 4-8 square pixel 15-1 stretch 23-12 sub picture 21-20, 22-21 sub-carrier 15-5 sub-picture 21-15, 22-15 subsystem id 18-6 s-video 15-1 t test mode 4-7
i - 2 index silicon motion ? , inc. SM731 confidential databook tft 29-10 tv 20-43 tv encoder 15-1, 20-21, 20-22 u user 20-34 v vendor 3-1 vendor id 3-1, 18-2 vertical blank 19-18 vertical sync 19-12, 19-16 video port 4-7 video processor 20-6 video window i 21-9, 21-30, 22-8, 22-31 y yuv to rgb 21-17, 22-18 z zv port 8-1


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